AR# 9928

Description

General Description:  

When an asynchronous FIFO (v2) is simulated, what do the following signals look like in simulation? 

AINIT 

DOUT 

FULL 

ALMOST_FULL 

EMPTY 

ALMOST_EMPTY 

WR_COUNT 

RD_COUNT

Solution

AINIT - Asserting AINIT will cause the following signals to be asserted: FULL, ALMOST_FULL, EMPTY, and ALMOST_EMPTY. Upon de-asserting this signal, the next rising edge of WR_CLK will de-assert FULL and ALMOST_FULL. (Asserting or de-asserting AINIT will not affect DOUT.) 

DOUT - In the simulation, this will be zero and will remain zero until a valid Read operation takes place. (RD_ACK acknowledgement will indicate the valid Read operation.) Once RD_EN is de-asserted, the last value in the queue (from the last read operation) will be reflected in DOUT. 

ALMOST_FULL - This signal will be asserted once the address reaches the second to last address (i.e., depth = 2^10 -1 = 1023, then valid depth is 0 to 1022. ALMOST_FULL will be asserted when data is written to address 1021.) 

FULL - This signal will be asserted when the you write to the last address (i.e., address 1022). 

For a description of RD_COUNT and WR_COUNT, please see (Xilinx Answer 9243).