AR# 9935

3.1i Foundation ISE - ERROR : (VHP__0855). top.vhf Line 57. An index of the formal port q of fd16ce is missing in instantiation.

Description

Keywords: ECS, macro, Project Navigator, ISE, VHP__0900

Urgency: Standard

General Description:
Project Navigator allows the instantiation of Xilinx Unified Library
macros in the VHDL/Verilog of the Schematic source. If the port
map is incorrect or not all pins are correctly connected, the following
errors are issued during synthesis:

XST --

ERROR : (VHP__0855). top.vhf Line 57. An index of the formal port q
of fd16ce is missing in instantiation.
ERROR : (VHP__0900). top.vhf Line 83. The label i4 is not declared.

FPGA Express --

Error: The entity 'TOP' depends on the package 'COMPONENTS'
which has been analyzed more recently. Please re-analyze the
source file for 'TOP' and try again. (LBR-28)

Solution

VHDL or Verilog:

Verify the port map for the declaration and instantion. Check bit
widths and pin names.

Schematic:

Verify that all pins on the macro are connected. Verify that the nets
are correctly labeled with the corresponding bit width.
AR# 9935
Date 01/15/2003
Status Archive
Type General Article