Zynq-7000 SoC Design Hub - Data Movers

Refer to the Zynq-7000 Design Overview Design Hub for information on System Design, Hardware Design, and Embedded Design.

IntroductionDate
 UG1046 - UltraFast Embedded Design Methodology Guide04/20/2018
 Zynq-7000 SoC Data Movers Wiki Page 
Key ConceptsDate
 UG1046 - System Data Movement in a Zynq-7000 SoC04/20/2018
 UG1046 - Peripherals in a Zynq-7000 SoC04/20/2018
 UG1046 - Data Flow in a Zynq-7000 SoC04/20/2018
TrainingDate
 Embedded Systems Design 

Design Resources

Design Resources

Targeted Reference DesignsDesign FilesDate
 DH0039 - ZC702 Evaluation Kit Design Hub 10/30/2019
 DH0040 - ZC706 Evaluation Kit Design Hub 10/30/2019
 AR62821 - Zynq-7000 SoC - Where Can I Find Data Mover Examples?  
Application NotesDesign FilesDate
 XAPP1183 - Implementing Analog Data Acquisition using the Zynq-7000 SoC Processing System with the XADC AXI InterfaceDesign Files11/18/2013
 XAPP1182 - System Monitoring using the Zynq-7000 Processing System with a Xilinx Analog-to-Digital Converter AXI InterfaceDesign Files11/18/2013
 XAPP1171 - PCI Express Endpoint-DMA Initiator SubsystemDesign Files11/04/2013
 XAPP1170 - Zynq-7000 SoC Accelerator for Floating-Point Matrix Multiplication using Vivado High-Level Synthesis (HLS)Design Files01/21/2016
 XAPP1082 - PS and PL Ethernet Performance and Jumbo Frame Support with PL Ethernet in the Zynq-7000 SoCDesign Files07/16/2018
White Papers Design FilesDate
 WP459 - Leveraging Data-Mover IPs for Data Movement in Zynq-7000 SoC Systems 01/13/2015
 WP445 - Enabling High-Speed Radio Designs with Xilinx FPGAs and SoCs 01/20/2014
Example DesignsDesign FilesDate
 AR50826 - Cache coherent CDMA transfers from block RAM to OCM  
Tech TipsDesign FilesDate
 Performance - Ehternet Packet Inspection - Linux - Redirecting Packets to PL and Cache Tech Tip  
 Performance - Ehternet Packet Inspection - Bare Metal - Redirecting Packets to PL Tech Tip  
 Spectrum Analyzer - Accelerating Software - Accelerating an FFT with ACP Coprocessor Tech Tip  
 AMS - XADC Signal Acquisition and DMA to L2 Cache & Compete Design Tech Tip  

Support Resources

Support Resources

Solution CentersDate
 AR52512 - Zynq-7000 SoC Solution Center08/25/2020
Xilinx Forums - Embedded SolutionsDate
 Embedded Processor System Design