Xilinx is now part ofAMDUpdated Privacy Policy

Memory Interfaces Design Hub - UltraScale DDR3/DDR4 Memory

This page covers Memory Interfacing in UltraScale Devices using the Memory Interface Generator (MIG) in the Vivado Design Suite

IntroductionDate
 XTP359 - Memory Interface UltraScale Design Checklist 
 PG150 - UltraScale Architecture FPGAs Memory IP Product Guide08/11/2021
 PG150 - Creating a Memory Interface Design using Vivado MIG08/11/2021
 Designing with UltraScale Memory IP09/16/2014
 AR58435 - Memory Interface UltraScale IP Release Notes03/31/2021
 Supported Memory Interfaces and Data Rates 
Design RequirementsDate
 PG150 - Input Clock Guidelines08/11/2021
 Memory Interface External Clocking03/15/2016
 UG583 - PCB Guidelines for DDR4 SDRAM06/03/2021
 UG583 - PCB Guidelines for DDR3 SDRAM06/03/2021
 PG150 - DDR4 Pin Rules08/11/2021
 PG150 - DDR3 Pin Rules08/11/2021
 UG899 - I/O Planning for UltraScale Device Memory IP06/16/2021
 PG150 - Designing for High Efficiency08/11/2021
 PG150 - Calculating User Specified Pattern Efficiency Using the Memory IP Performance Testbench08/11/2021
 Designing with UltraScale Memory IP09/16/2014
 UG899 - Importing I/O Ports for an Existing Pin-Out/Board06/16/2021
Interfacing to Memory Interface IPDate
 PG150 - Interfacing to the Memory IP User Interface08/11/2021
 PG150 - Interfacing to the PHY Only Interface08/11/2021
 PG150 - Interfacing to the AXI4 Slave Interface08/11/2021
Simulating Memory Interface IPDate
 PG150 - Simulating the Memory IP Example Design08/11/2021
 DH0010 - Vivado Logic Simulation Design Hub06/16/2021
Frequently Asked Questions (FAQ)Date
 AR62920 - Memory IP UltraScale Solution Center - Frequently Asked Questions (FAQ) 

Additional Learning Materials

Additional Learning Materials