UltraScale and UltraScale+ GTY Transceivers

Getting StartedDesign ResourcesSupport ResourcesTransceiver IP Resources

Refer to the High Speed Serial Product Page for more information on Xilinx GTY Transceivers.

High-Speed Serial I/O Designer's GuideDate
 Basic Concepts 
 Purpose of SERDES 
 History of SERDES 
 Alignment, Encoding, Emphasis, Buffers, Channel Bonding and Clock Correction 
UltraScale GTY Transceivers User GuideDate
 UG578 - RX Byte and Word Alignment09/20/2017
 UG578 - RX 8B/10B Decoder09/20/2017
 UG578 - Buffer Control09/20/2017
 UG578 - RX Clock Correction09/20/2017
 UG578 - RX Channel Bonding09/20/2017
 UG578 - RX Synchronous Gearbox09/20/2017
 UG578 - RX Clock Data Recovery (CDR)09/20/2017

Product Specifications

Product Specifications

UltraScale Transceiver Wizard

UltraScale Transceiver Wizard

Refer to the UltraScale FPGAs Transceivers Wizard IP Product Page for more information regarding this IP.

Using the Wizard IP CoreDate
 PG182 - Overview11/11/2019
 PG182 - Designing with the Core11/11/2019
 PG182 - Design Flow Steps11/11/2019
 PG182 - Example Design11/11/2019
 PG182 - Test Bench Usage11/11/2019
 AR70679 - UltraScale Transceiver Wizard - Release Notes and Known Issues08/27/2020