UltraScale and UltraScale+ GTH Transceivers

Getting StartedDesign ResourcesSupport ResourcesTransceiver IP Resources

Refer to the High Speed Serial Product Page for more information on Xilinx GTY Transceivers.

High-Speed Serial I/O Designer's GuideDate
 Basic Concepts 
 Purpose of SERDES 
 History of SERDES 
 Alignment, Encoding, Emphasis, Buffers, Channel Bonding and Clock Correction 
UltraScale GTH Transceivers User GuideDate
 UG576 - RX Byte and Word Alignment08/26/2019
 UG576 - RX 8B/10B Decoder08/26/2019
 UG576 - Buffer Control08/26/2019
 UG576 - RX Clock Correction08/26/2019
 UG576 - RX Channel Bonding08/26/2019
 UG576 - RX Synchronous Gearbox08/26/2019
 UG576 - RX Clock Data Recovery (CDR)08/26/2019

Product Specifications

Product Specifications

The characterization reports for UltraScale and UltraScale+ devices are confidential. Please contact a Xilinx Specialist for more information.

Supported ProtocolsDate
 DS922 - Kintex UltraScale+ - GTH Transceiver Protocol List07/12/2019
 DS893 - Virtex UltraScale - GTH Transceiver Protocol List05/23/2019
 DS892 - Kintex UltraScale - GTH Transceiver Protocol List09/22/2020
Max Data RatesDate
 DS922 - Kintex UltraScale+ - GTH Transceiver Performance07/12/2019
 DS893 - Virtex UltraScale - GTH Transceiver Performance05/23/2019
 DS892 - Kintex UltraScale - GTH Transceiver Performance09/22/2020

UltraScale Transceiver Wizard

UltraScale Transceiver Wizard

Refer to the UltraScale FPGAs Transceivers Wizard IP Product Page for more information regarding this IP.

Using the Wizard IP CoreDate
 AR70679 - UltraScale Transceiver Wizard - Release Notes and Known Issues08/27/2020
 PG182 - Overview11/11/2019
 PG182 - Designing with the Core11/11/2019
 PG182 - Design Flow Steps11/11/2019
 PG182 - Example Design11/11/2019
 PG182 - Test Bench Usage11/11/2019