Zynq UltraScale+ RFSoC Design Overview

Design Resources

Design Resources

User Guides and TutorialsDesign FilesDate
 Zynq UltraScale+ Device Packaging and Pinouts Product Specification 07/12/2019
 UltraScale Architecture PCB Design User Guide 08/29/2019
 Xilinx Power Estimator User Guide 12/20/2018
 UltraScale Architecture GTY Transceivers User Guide 09/20/2017
 UltraScale FPGAs Transceivers Wizard v1.7 Product Guide for Vivado Design Suite 06/21/2019
 RF Analyzer Tutorial  
White PapersDesign FilesDate
 An Adaptable Direct RF-Sampling Solution 02/20/2019
 Integrated SD-FEC in Zynq UltraScale+ RFSoCs for Higher Throughput and Power Efficiency 05/29/2018
 Understanding Key Parameters for RF-Sampling Data Converters 02/20/2019
ReportsDesign FilesDate
 Zynq UltraScale+ Characterization Reports  
Design AdvisoriesDesign FilesDate
 Design Advisory for Zynq UltraScale+ MPSoC/RFSoC: 2019.1 XilSKeyPUF Registration is incorrect 08/08/2019
 Design Advisory for Zynq UltraScale+ MPSoC/RFSoC: Encrypt Only Boot Mode - Unauthenticated Boot and Partition Headers 08/08/2019
 Design Advisory for Zynq UltraScale+ MPSoC/RFSoC - PS LPDDR4 DRAM devices require WDQS Control to be enabled 07/11/2019
 Design Advisory for Zynq UltraScale+ MPSoC/RFSoC: A glitch might be observed on the PMU GPO1[2] (MIO34) following assertion of PS_POR_B 04/26/2019
 Design Advisory for Zynq UltraScale+ MPSoC/RFSoC - MIO26 cannot be used for GEM TSU_REF_CLK 04/05/2019
 Design Advisory for Zynq UltraScale+ MPSoC/RFSoC Processing System - MIO Slew and Input Type register settings incorrect 04/05/2019
 Design Advisory ZCU104 and ZCU111 - Infineon IRPS5401 has a drive signal of 5V for an external power stage 01/17/2019
 Are Xilinx Zynq-7000 and Zynq UltraScale+ MPSoC & RFSoC devices affected by the Meltdown and Spectre vulnerabilities? 05/15/2018
Design HubsDesign FilesDate
 Zynq UltraScale+ MPSoC Design Overview 08/30/2019
Application NotesDesign FilesDate
 Aurora 8B10B for GTY UltraScale+, Zynq UltraScale+ MPSoC and RFSoCDesign Files06/06/2018