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Versal ACAP Design Process Documentation

Xilinx provides a breadth of documentation, resources, and methodologies to accelerate your development on the Versal architecture. If you’re not sure where to begin with Versal ACAPs, the Versal Design Flow Assistant is an interactive guide to help you create a development strategy, while the Design Process Hubs are a visual and streamlined reference to all Versal documentation by design process. For the complete list of Versal training courses, see General Versal Training.

AI Engine Development: Provides guidance for creating the AI Engine graph and kernels, library usage, simulation debugging and profiling, and algorithm development. Also includes the integration of the PL and AI Engine kernels.

Guided
Overview Develop the AI Engine kernel, and graph Designing the AI Engine and Graph Designing the AI Engine and Graph Testing and Validating AI Engine Kernels and Graph in Vitis™ Libraries for AI Engine Integrating PL and AI Engine Kernels and PS Host Application ... Testing and Validating AI Engine kernels and Graph in Vitis™ Test and Validate the Design Using Hardware Emulation Integrating PL and AI Engine Kernels and PS Host Application in Vitis™ Testing and Validating the Design in Hardware Test and validate the design using hardware emulation Partitioning the AI Engine array Versal Design Partitioning (incl. AI Engine array) Verifying the algorithm, testing and validating AI Engine ker... Verifying the algorithm, testing and validating AI Engine kernels in Vitis™ Debugging Performance analysis, profiling Debugging in HW Debugging Performance analysis, profiling Performance analysis, profiling Debugging Debugging Develop the AI Engine kernel and graph Performance analysis and optimization Performance analysis and optimization Training Modules Mapping GMIO and PLIO ports in the graph Integrating PL kernels into the graph Programming the PS host application Performance analysis System linking System packaging and deployment Designing the AI Engine and Graph Testing and Validating the Design in Hardware Debugging in HW Performance analysis, profiling Mapping GMIO and PLIO ports in the graph Integrating PL kernels into the graph Programming the PS host application Performance analysis System linking System packaging and deployment Develop in MATLAB and Simulink using Vitis Model Composer
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