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Versal ACAP Design Process Documentation

Xilinx provides a breadth of documentation, resources, and methodologies to accelerate your development on the Versal architecture. If you’re not sure where to begin with Versal ACAPs, the Versal Design Flow Assistant is an interactive guide to help you create a development strategy, while the Design Process Hubs are a visual and streamlined reference to all Versal documentation by design process. For the complete list of Versal training courses, see General Versal Training.

AI Engine Development: Provides guidance for creating the AI Engine graph and kernels, library usage, simulation debugging and profiling, and algorithm development. Also includes the integration of the PL and AI Engine kernels.

Guided
Overview Develop AI Engine Kernels and Graph Simulate and Debug the AI Engine Graph Test Hardware and Debug the AI Engine Graph Versal Design Partitioning (incl. AI Engine Array) Verify the Algorithm, Test, and Validate AI Engine Kernels in Vitis™ Debugging Develop the AI Engine Kernel and Graph Libraries for AI Engine Performance Analysis and Optimization Overview Training Modules Create a Verification Subsystem for Hardware Testing Integrate AIE and Other Domains with the Verification Subsystem Validate Subsystem Using Hardware Emulation Test and Debug AIE Graph in Hardware Develop in MATLAB and Simulink Using Vitis Model Composer
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