Xilinx provides a breadth of documentation, resources, and methodologies to accelerate your development on the Versal architecture. If you’re not sure where to begin with Versal ACAPs, the Versal Design Flow Assistant is an interactive guide to help you create a development strategy, while the Design Process Hubs are a visual and streamlined reference to all Versal documentation by design process. For the complete list of Versal training courses, see General Versal Training.
HW, IP & Platform Development: Provides guidance for creating the PL IP blocks for the hardware platform, creating PL kernels (HLS or RTL), subsystem functional simulation, and evaluating the Vivado timing, resource and power closure. Also involves developing the hardware platform (fixed or extensible) for system integration.
|Designing with the Versal ACAP: Architecture and Methodology|
|Designing with the Versal ACAP: NoC|
|High-Level Synthesis with the Vitis HLS Tool|
|Designing with Versal AI Engine 1: Architecture and Design Flow|
|Designing with Versal AI Engine 2: Graph Programming with AI Engine Kernels|
|Designing with Versal AI Engine 3: Kernel Programming and Optimization|