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Versal Design Processes Documentation

Xilinx provides a breadth of documentation, resources, and methodologies to accelerate your development on the Versal architecture. If you’re not sure where to begin with Versal ACAPs, the Versal Design Flow Assistant is an interactive guide to help you create a development strategy, while the Design Process Hubs are a visual and streamlined reference to all Versal documentation by design process. For the complete list of Versal training courses, see General Versal Training

Machine Learning and Data Science: Provides guidance for importing a machine learning model from a Caffe or TensorFlow framework onto Vitis AI, then optimize and evaluate its effectiveness.

Create Custom PL IP Blocks and RTL Modules Overview Create PL Kernels Using HLS ML Inference Block design creation Training Modules Use Vitis HLS libraries Debug as necessary Programming for Vitis™ HLS Compile the fixed-point model into the binary Performance optimization Run the compiled model with API code to deploy Versal TM or Vitis TM Performance optimization Quantize the floating-point model to fixed-point model Performance optimization Optimize the model for speed Verifying the PL kernel Test and validate during runtime Use Vitis HLS libraries Create custom platform with DPU
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