Versal ACAP Design Flow Assistant

Welcome!

These pages are intended to help Xilinx customers better understand the design flows and details for successfully building Versal™ ACAP designs.

The questions below are designed to guide you to detailed reference guides that are specific to your intended design needs, and to provide links to more detailed information.

Design Flow Questions

If your design plan incorporates any of the following, click Yes. If none of this applies, click No. You will then be asked a series of questions to launch the appropriate quick reference guide to provide more complete design details.

  • Are you targeting AI Engine-based devices?
  • Do you want to begin development on individual subsystems on a Xilinx development board, or before a custom platform is available? 
  • Will there be non-FPGA designers creating PL or AI Engine content? 

About the Versal ACAP Design Flows 

There are two design flows for Versal ACAP: the traditional design flow and the platform-based design flow.  The following provides more detailed information about these two design flows.

Traditional Design Flow

In the traditional design flow, the entire PL portion of the system is defined in a single Vivado™ project. This project must include the foundational Versal hardware IP blocks (e.g., CIPS, NoC, I/O controllers) and any other custom RTL and IP blocks needed for the project. Design sources are added to the Vivado tools and compiled through the Vivado implementation flow. If the system consists of PL components only, the Vivado tools are used to generate a programmable device image (PDI) to program the Versal device. If the system also includes embedded software content, the software application is developed in the Vitis™ environment on top of the fixed hardware design exported from Vivado. This flow is very similar to the one traditionally used for Zynq® UltraScale+™ MPSoCs.

Platform-based Design Flow

In the platform-based design flow, the system is divided in two distinct elements: the platform and the processing system. The platform is a well-formalized design resource that contains the foundational Versal hardware IP blocks (e.g., CIPS, NoC, I/O controllers) and software features (e.g., domains, device tree, OS) upon which a complete working system can be built and integrated. The hardware part of the platform is a dedicated Vivado project containing the minimum necessary hardware IP blocks. The software components are packaged with the hardware to create a custom platform. The processing system consists of PS, PL and optional AI Engine features that implement the main functionality of the system. These different elements can be created with the Vivado tools or the Vitis environment. Once created, they are integrated to the platform using the Vitis environment. This flow promotes concurrent development of the different elements of the system and greatly facilitates the integration process of heterogenous systems.

Please see the Versal ACAP Design Guide for more detailed information.