Burst Clock Data Recovery for 1.25G/2.5G PON Applications in UltraScale Devices (XAPP1277)

Document ID: XAPP1277
Release Date: 2024-01-05
Revision: 1.2 English

Summary
Introduction
Features
Overview of a PON Network
Circuit Description and Usage Model
BCDR and PHY Configuration
BCDR Simulation Test Bench
Start the Simulation
Simulation Test Results
Hardware Test Bench on the KCU1250 Board
Device Sizing and Recommendations
Reference Design
References
Revision History
Please Read: Important Legal Notices

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