Virtex UltraScale+ FPGAs GTM Transceivers Wizard LogiCORE IP Product Guide (PG315) - 1.0 English

Document ID: PG315
Release Date: 2022-05-04
Version: 1.0 English

Introduction
Features
IP Facts
Overview
Navigating Content by Design Processes
Applications
Licensing and Ordering
Product Specification
Wizard Basic Concepts
Performance
Port Descriptions
GTM Controller Helper Logic
Sampled Eye Scan Functionality
Reset Controller Helper Block Ports
Reset Controller Helper Block Transceiver Interface Ports
Reset Controller Helper Block Tie-off Ports
Transmitter User Clocking Network Helper Block Ports
Receiver User Clocking Network Helper Block Ports
Designing with the Core
General Design Guidelines
Use the Example Design
Registering Signals
Recognize Timing Critical Signals
Make Only Allowed Modifications
Reset Controller Helper Block
Reset State Machines
Transmitter User Clocking Network Helper Block
Receiver User Clocking Network Helper Block
Transcode Helper Block
Port Descriptions
Supported Modes
Designing With Multi-Duals
Design Flow Steps
Customizing and Generating the Core
Vivado IDE Customization Parameters
Basic Tab
Physical Resources Tab
Optional Features Tab
FEC Options Tab
Output Generation
Simulation
Example Design
Purpose of the Example Design
Example Design Ports
Link Status and Initialization
Link Status Logic
Initialization Module
Adapting the Example Design
Multi Rate GTM Extensions
Rate Change Port Description
Rate Change Protocol Description
Rate Table Interface Description
GTM Port Control Interface Description
IP Creation
Rate Table Creation and Association
Multi-Rate Example Design
Limitations of the Example Design
Test Bench
Simulating the Example Design
PAM4 Signal Inference in GTM Transceivers
VHDL GTM Transceiver Parent IP Simulation Workarounds
Method 1
Method 2
Simulation Behavior
Additional Resources and Legal Notices
Xilinx Resources
Documentation Navigator and Design Hubs
References
Training Resources
Revision History
Please Read: Important Legal Notices

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