Resource Utilization for Clocking Wizard v6.0

Vivado Design Suite Release 2020.2

Interpreting the results

This page contains resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Kintex-7

Part Information Configuration Parameters Resource Utilization
Device Package Speed Grade Configuration Name
PRIMITIVE
USE_FREQ_SYNTH
USE_PHASE_ALIGNMENT
USE_MIN_POWER
USE_DYN_RECONFIG
JITTER_SEL
PRIM_IN_FREQ
IN_JITTER_UNITS
SECONDARY_IN_FREQ
SECONDARY_SOURCE
JITTER_OPTIONS
CLKIN1_UI_JITTER
PRIM_IN_JITTER
SECONDARY_IN_JITTER
CLKIN1_JITTER_PS
CLKIN2_JITTER_PS
CLKOUT1_USED
CLKOUT2_USED
CLKOUT3_USED
CLKOUT4_USED
CLKOUT5_USED
CLKOUT6_USED
CLKOUT7_USED
CLKOUT1_REQUESTED_OUT_FREQ
CLKOUT1_REQUESTED_PHASE
CLKOUT2_REQUESTED_OUT_FREQ
CLKOUT2_REQUESTED_PHASE
CLKOUT3_REQUESTED_OUT_FREQ
CLKOUT3_REQUESTED_PHASE
CLKOUT4_REQUESTED_OUT_FREQ
CLKOUT4_REQUESTED_PHASE
CLKOUT5_REQUESTED_OUT_FREQ
CLKOUT5_REQUESTED_PHASE
CLKOUT6_REQUESTED_OUT_FREQ
CLKOUT6_REQUESTED_PHASE
CLKOUT7_REQUESTED_OUT_FREQ
CLKOUT7_REQUESTED_PHASE
PRIM_SOURCE
CLKOUT1_DRIVES
CLKOUT2_DRIVES
CLKOUT3_DRIVES
CLKOUT4_DRIVES
CLKOUT5_DRIVES
CLKOUT6_DRIVES
CLKOUT7_DRIVES
FEEDBACK_SOURCE
USE_LOCKED
LOCKED_PORT
POWER_DOWN_PORT
RESET_TYPE
INTERFACE_SELECTION
PHASE_DUTY_CONFIG
Fixed clocks (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xc7k325t fbg676 -2 resource_utils_1 MMCM true true true true Max_I_Jitter 391 Units_UI 100.000 Single_ended_clock_capable_pin PS 870 0.010000 0.000000 236 100 true true true true true true true 156 116 44 170 39 174 39 266 39 155 39 141 36 11 Global_buffer BUFGCE BUFGCE BUFGCE BUFGCE BUFGCE BUFGCE BUFGCE FDBK_AUTO_OFFCHIP true locked power_down ACTIVE_HIGH Enable_AXI clk_in1=391 s_axi_aclk=100 3028 1552 8 0 0 PRODUCTION 1.12 2017-02-17
xc7k325t fbg676 -2 resource_utils_2 MMCM true true true true Max_I_Jitter 391 Units_UI 100.000 Single_ended_clock_capable_pin PS 870 0.010000 0.000000 236 100 true true true true true true true 156 116 44 170 39 174 39 266 39 155 39 141 36 11 Global_buffer BUFGCE BUFGCE BUFGCE BUFGCE BUFGCE BUFGCE BUFGCE FDBK_AUTO_OFFCHIP true locked ACTIVE_HIGH Enable_AXI true clk_in1=391 s_axi_aclk=100 13545 1574 38 0 0 PRODUCTION 1.12 2017-02-17

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