Performance and Resource Utilization for Discrete Fourier Transform v4.1

Vivado Design Suite Release 2019.2

Interpreting the results

This page contains maximum frequency and resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Data is provided for the following device families:

Kintex-7

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Data_Width
Speed_Optimization
Synchronous_Clear
Support_Size_1536
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xc7k480t ffg901 -1 k7_1_d16_area_1536 16 Area false true CLK 341 3583 4559 16 4 4 PRODUCTION 1.12 2017-02-17
xc7k480t ffg901 -1 k7_1_d16_area_no1536 16 Area false false CLK 341 3576 4595 16 3 4 PRODUCTION 1.12 2017-02-17
xc7k480t ffg901 -1 k7_1_d16_spd_1536 16 Speed false true CLK 341 3583 4559 16 4 4 PRODUCTION 1.12 2017-02-17
xc7k480t ffg901 -1 k7_1_d16_spd_no1536 16 Speed false false CLK 341 3576 4595 16 3 4 PRODUCTION 1.12 2017-02-17
xc7k480t ffg901 -1 k7_1_d8_area_1536 8 Area false true CLK 347 2842 3483 16 4 4 PRODUCTION 1.12 2017-02-17
xc7k480t ffg901 -1 k7_1_d8_area_no1536 8 Area false false CLK 341 2839 3488 16 3 4 PRODUCTION 1.12 2017-02-17

Kintex UltraScale

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Data_Width
Speed_Optimization
Synchronous_Clear
Support_Size_1536
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcku115 flva1517 -1 ku_1_d16_area_1536 16 Area false true CLK 396 3449 4602 16 4 4 PRODUCTION 1.26 12-04-2018
xcku115 flva1517 -1 ku_1_d16_area_no1536 16 Area false false CLK 402 3491 4625 16 3 4 PRODUCTION 1.26 12-04-2018
xcku115 flva1517 -1 ku_1_d16_spd_1536 16 Speed false true CLK 396 3449 4602 16 4 4 PRODUCTION 1.26 12-04-2018
xcku115 flva1517 -1 ku_1_d16_spd_no1536 16 Speed false false CLK 402 3491 4625 16 3 4 PRODUCTION 1.26 12-04-2018
xcku115 flva1517 -1 ku_1_d8_area_1536 8 Area false true CLK 402 2814 3494 16 4 4 PRODUCTION 1.26 12-04-2018
xcku115 flva1517 -1 ku_1_d8_area_no1536 8 Area false false CLK 402 2825 3534 16 3 4 PRODUCTION 1.26 12-04-2018

Kintex UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Data_Width
Speed_Optimization
Synchronous_Clear
Support_Size_1536
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcku13p ffve900 -1 kup_1_d16_area_1536 16 Area false true CLK 555 3752 4874 16 4 4 PRODUCTION 1.27 08-13-2019
xcku13p ffve900 -1 kup_1_d16_area_no1536 16 Area false false CLK 560 3797 5041 16 3 4 PRODUCTION 1.27 08-13-2019
xcku13p ffve900 -1 kup_1_d16_spd_1536 16 Speed false true CLK 555 3752 4874 16 4 4 PRODUCTION 1.27 08-13-2019
xcku13p ffve900 -1 kup_1_d16_spd_no1536 16 Speed false false CLK 560 3797 5041 16 3 4 PRODUCTION 1.27 08-13-2019
xcku13p ffve900 -1 kup_1_d8_area_1536 8 Area false true CLK 555 3010 3824 16 4 4 PRODUCTION 1.27 08-13-2019
xcku13p ffve900 -1 kup_1_d8_area_no1536 8 Area false false CLK 566 3062 3920 16 3 4 PRODUCTION 1.27 08-13-2019

Virtex-7

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Data_Width
Speed_Optimization
Synchronous_Clear
Support_Size_1536
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xc7vx690t ffg1157 -1 v7_1_d16_area_1536 16 Area false true CLK 336 3536 4607 16 4 4 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 v7_1_d16_area_no1536 16 Area false false CLK 341 3589 4634 16 3 4 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 v7_1_d16_spd_1536 16 Speed false true CLK 336 3536 4607 16 4 4 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 v7_1_d16_spd_no1536 16 Speed false false CLK 341 3589 4634 16 3 4 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 v7_1_d8_area_1536 8 Area false true CLK 341 2831 3553 16 4 4 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 v7_1_d8_area_no1536 8 Area false false CLK 347 2842 3487 16 3 4 PRODUCTION 1.11 2014-09-11

Virtex UltraScale

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Data_Width
Speed_Optimization
Synchronous_Clear
Support_Size_1536
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcvu160 flgb2104 -1 vu_1_d16_area_1536 16 Area false true CLK 374 3410 4636 16 4 4 PRODUCTION 1.27 12-04-2018
xcvu160 flgb2104 -1 vu_1_d16_area_no1536 16 Area false false CLK 402 3483 4640 16 3 4 PRODUCTION 1.27 12-04-2018
xcvu160 flgb2104 -1 vu_1_d16_spd_1536 16 Speed false true CLK 374 3410 4636 16 4 4 PRODUCTION 1.27 12-04-2018
xcvu160 flgb2104 -1 vu_1_d16_spd_no1536 16 Speed false false CLK 402 3483 4640 16 3 4 PRODUCTION 1.27 12-04-2018
xcvu160 flgb2104 -1 vu_1_d8_area_1536 8 Area false true CLK 402 2840 3724 16 4 4 PRODUCTION 1.27 12-04-2018
xcvu160 flgb2104 -1 vu_1_d8_area_no1536 8 Area false false CLK 407 2847 3688 16 3 4 PRODUCTION 1.27 12-04-2018

Virtex UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Data_Width
Speed_Optimization
Synchronous_Clear
Support_Size_1536
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcvu9p flgb2104 -1 vup_1_d16_area_1536 16 Area false true CLK 566 3802 4927 16 4 4 PRODUCTION 1.26 08-13-2019
xcvu9p flgb2104 -1 vup_1_d16_area_no1536 16 Area false false CLK 566 3849 4915 16 3 4 PRODUCTION 1.26 08-13-2019
xcvu9p flgb2104 -1 vup_1_d16_spd_1536 16 Speed false true CLK 566 3802 4927 16 4 4 PRODUCTION 1.26 08-13-2019
xcvu9p flgb2104 -1 vup_1_d16_spd_no1536 16 Speed false false CLK 566 3849 4915 16 3 4 PRODUCTION 1.26 08-13-2019
xcvu9p flgb2104 -1 vup_1_d8_area_1536 8 Area false true CLK 566 3050 3893 16 4 4 PRODUCTION 1.26 08-13-2019
xcvu9p flgb2104 -1 vup_1_d8_area_no1536 8 Area false false CLK 566 3081 3860 16 3 4 PRODUCTION 1.26 08-13-2019

Zynq UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Data_Width
Speed_Optimization
Synchronous_Clear
Support_Size_1536
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xczu9eg ffvb1156 -1 zup_1_d16_area_1536 16 Area false true CLK 560 3774 4985 16 4 4 PRODUCTION 1.26 08-13-2019
xczu9eg ffvb1156 -1 zup_1_d16_area_no1536 16 Area false false CLK 560 3795 4974 16 3 4 PRODUCTION 1.26 08-13-2019
xczu9eg ffvb1156 -1 zup_1_d16_spd_1536 16 Speed false true CLK 560 3774 4985 16 4 4 PRODUCTION 1.26 08-13-2019
xczu9eg ffvb1156 -1 zup_1_d16_spd_no1536 16 Speed false false CLK 560 3795 4974 16 3 4 PRODUCTION 1.26 08-13-2019
xczu9eg ffvb1156 -1 zup_1_d8_area_1536 8 Area false true CLK 560 3034 3825 16 4 4 PRODUCTION 1.26 08-13-2019
xczu9eg ffvb1156 -1 zup_1_d8_area_no1536 8 Area false false CLK 555 3027 3851 16 3 4 PRODUCTION 1.26 08-13-2019

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