Performance and Resource Utilization for Divider Generator v5.1

Vivado Design Suite Release 2019.1

Interpreting the results

This page contains maximum frequency and resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Data is provided for the following device families:

Kintex-7

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
algorithm_type
dividend_and_quotient_width
divisor_width
remainder_type
fractional_width
operand_sign
clocks_per_division
FlowControl
latency_configuration
latency
Clock Input Fmax (MHz) LUTs FFs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xc7k480t ffg901 -1 k7_1_hr_10_by_14_f2 High_Radix 10 14 Fractional 2 Signed 1 NonBlocking Manual 17 aclk 396 242 441 7 0 1 PRODUCTION 1.12 2017-02-17
xc7k480t ffg901 -1 k7_1_hr_36_by_36_f2 High_Radix 36 36 Fractional 2 Signed 1 NonBlocking Automatic aclk 396 596 1208 13 0 1 PRODUCTION 1.12 2017-02-17
xc7k480t ffg901 -1 k7_1_hr_54_by_50_f28 High_Radix 54 50 Fractional 28 Signed 1 NonBlocking Automatic aclk 396 950 1827 16 0 1 PRODUCTION 1.12 2017-02-17
xc7k480t ffg901 -1 k7_1_hr_54_by_50_f28_lowlat High_Radix 54 50 Fractional 28 Signed 1 NonBlocking Manual 8 aclk 72 824 267 16 0 1 PRODUCTION 1.12 2017-02-17
xc7k480t ffg901 -1 k7_1_lm LutMult 11 12 Remainder 12 Unsigned 1 NonBlocking Automatic aclk 374 17 127 2 3 0 PRODUCTION 1.12 2017-02-17
xc7k480t ffg901 -1 k7_1_r2_32_by_32_r32 Radix2 32 32 Remainder 32 Signed 1 NonBlocking Automatic aclk 456 1280 3334 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k480t ffg901 -1 k7_1_r2_8_by_8_r8 Radix2 8 8 Remainder 8 Signed 1 NonBlocking Automatic aclk 636 125 262 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k480t ffg901 -1 k7_1_r2_8_by_8_r8_clk2 Radix2 8 8 Remainder 8 Signed 2 NonBlocking Automatic aclk 467 119 207 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k480t ffg901 -1 k7_1_r2_8_by_8_r8_clk8 Radix2 8 8 Remainder 8 Signed 8 NonBlocking Automatic aclk 538 64 134 0 0 0 PRODUCTION 1.12 2017-02-17

Kintex UltraScale

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
algorithm_type
dividend_and_quotient_width
divisor_width
remainder_type
fractional_width
operand_sign
clocks_per_division
FlowControl
latency_configuration
latency
Clock Input Fmax (MHz) LUTs FFs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xcku115 flva1517 -1 ku_1_hr_10_by_14_f2 High_Radix 10 14 Fractional 2 Signed 1 NonBlocking Manual 17 aclk 456 221 441 7 0 1 PRODUCTION 1.26 12-04-2018
xcku115 flva1517 -1 ku_1_hr_36_by_36_f2 High_Radix 36 36 Fractional 2 Signed 1 NonBlocking Automatic aclk 456 511 1208 13 0 1 PRODUCTION 1.26 12-04-2018
xcku115 flva1517 -1 ku_1_hr_54_by_50_f28 High_Radix 54 50 Fractional 28 Signed 1 NonBlocking Automatic aclk 456 807 1827 16 0 1 PRODUCTION 1.26 12-04-2018
xcku115 flva1517 -1 ku_1_hr_54_by_50_f28_lowlat High_Radix 54 50 Fractional 28 Signed 1 NonBlocking Manual 8 aclk 95 741 250 16 0 1 PRODUCTION 1.26 12-04-2018
xcku115 flva1517 -1 ku_1_lm LutMult 11 12 Remainder 12 Unsigned 1 NonBlocking Automatic aclk 424 18 127 2 3 0 PRODUCTION 1.26 12-04-2018
xcku115 flva1517 -1 ku_1_r2_32_by_32_r32 Radix2 32 32 Remainder 32 Signed 1 NonBlocking Automatic aclk 402 1280 3334 0 0 0 PRODUCTION 1.26 12-04-2018
xcku115 flva1517 -1 ku_1_r2_8_by_8_r8 Radix2 8 8 Remainder 8 Signed 1 NonBlocking Automatic aclk 664 123 262 0 0 0 PRODUCTION 1.26 12-04-2018
xcku115 flva1517 -1 ku_1_r2_8_by_8_r8_clk2 Radix2 8 8 Remainder 8 Signed 2 NonBlocking Automatic aclk 549 116 207 0 0 0 PRODUCTION 1.26 12-04-2018
xcku115 flva1517 -1 ku_1_r2_8_by_8_r8_clk8 Radix2 8 8 Remainder 8 Signed 8 NonBlocking Automatic aclk 588 63 134 0 0 0 PRODUCTION 1.26 12-04-2018

Kintex UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
algorithm_type
dividend_and_quotient_width
divisor_width
remainder_type
fractional_width
operand_sign
clocks_per_division
FlowControl
latency_configuration
latency
Clock Input Fmax (MHz) LUTs FFs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xcku13p ffve900 -1 kup_1_hr_10_by_14_f2 High_Radix 10 14 Fractional 2 Signed 1 NonBlocking Manual 17 aclk 571 225 443 7 0 1 PRODUCTION 1.23 03-18-2019
xcku13p ffve900 -1 kup_1_hr_36_by_36_f2 High_Radix 36 36 Fractional 2 Signed 1 NonBlocking Automatic aclk 571 543 1208 13 0 1 PRODUCTION 1.23 03-18-2019
xcku13p ffve900 -1 kup_1_hr_54_by_50_f28 High_Radix 54 50 Fractional 28 Signed 1 NonBlocking Automatic aclk 571 864 1827 16 0 1 PRODUCTION 1.23 03-18-2019
xcku13p ffve900 -1 kup_1_hr_54_by_50_f28_lowlat High_Radix 54 50 Fractional 28 Signed 1 NonBlocking Manual 8 aclk 131 756 250 16 0 1 PRODUCTION 1.23 03-18-2019
xcku13p ffve900 -1 kup_1_lm LutMult 11 12 Remainder 12 Unsigned 1 NonBlocking Automatic aclk 615 18 127 2 3 0 PRODUCTION 1.23 03-18-2019
xcku13p ffve900 -1 kup_1_r2_32_by_32_r32 Radix2 32 32 Remainder 32 Signed 1 NonBlocking Automatic aclk 839 1278 3334 0 0 0 PRODUCTION 1.23 03-18-2019
xcku13p ffve900 -1 kup_1_r2_8_by_8_r8 Radix2 8 8 Remainder 8 Signed 1 NonBlocking Automatic aclk 872 124 262 0 0 0 PRODUCTION 1.23 03-18-2019
xcku13p ffve900 -1 kup_1_r2_8_by_8_r8_clk2 Radix2 8 8 Remainder 8 Signed 2 NonBlocking Automatic aclk 790 118 207 0 0 0 PRODUCTION 1.23 03-18-2019
xcku13p ffve900 -1 kup_1_r2_8_by_8_r8_clk8 Radix2 8 8 Remainder 8 Signed 8 NonBlocking Automatic aclk 866 63 134 0 0 0 PRODUCTION 1.23 03-18-2019

Virtex-7

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
algorithm_type
dividend_and_quotient_width
divisor_width
remainder_type
fractional_width
operand_sign
clocks_per_division
FlowControl
latency_configuration
latency
Clock Input Fmax (MHz) LUTs FFs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xc7vx690t ffg1157 -1 v7_1_hr_10_by_14_f2 High_Radix 10 14 Fractional 2 Signed 1 NonBlocking Manual 17 aclk 396 243 441 7 0 1 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 v7_1_hr_36_by_36_f2 High_Radix 36 36 Fractional 2 Signed 1 NonBlocking Automatic aclk 396 596 1208 13 0 1 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 v7_1_hr_54_by_50_f28 High_Radix 54 50 Fractional 28 Signed 1 NonBlocking Automatic aclk 396 950 1827 16 0 1 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 v7_1_hr_54_by_50_f28_lowlat High_Radix 54 50 Fractional 28 Signed 1 NonBlocking Manual 8 aclk 72 807 267 16 0 1 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 v7_1_lm LutMult 11 12 Remainder 12 Unsigned 1 NonBlocking Automatic aclk 374 17 127 2 3 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 v7_1_r2_32_by_32_r32 Radix2 32 32 Remainder 32 Signed 1 NonBlocking Automatic aclk 450 1280 3334 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 v7_1_r2_8_by_8_r8 Radix2 8 8 Remainder 8 Signed 1 NonBlocking Automatic aclk 636 125 262 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 v7_1_r2_8_by_8_r8_clk2 Radix2 8 8 Remainder 8 Signed 2 NonBlocking Automatic aclk 478 119 207 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 v7_1_r2_8_by_8_r8_clk8 Radix2 8 8 Remainder 8 Signed 8 NonBlocking Automatic aclk 560 64 134 0 0 0 PRODUCTION 1.11 2014-09-11

Virtex UltraScale

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
algorithm_type
dividend_and_quotient_width
divisor_width
remainder_type
fractional_width
operand_sign
clocks_per_division
FlowControl
latency_configuration
latency
Clock Input Fmax (MHz) LUTs FFs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xcvu160 flgb2104 -1 vu_1_hr_10_by_14_f2 High_Radix 10 14 Fractional 2 Signed 1 NonBlocking Manual 17 aclk 456 219 441 7 0 1 PRODUCTION 1.27 12-04-2018
xcvu160 flgb2104 -1 vu_1_hr_36_by_36_f2 High_Radix 36 36 Fractional 2 Signed 1 NonBlocking Automatic aclk 456 511 1208 13 0 1 PRODUCTION 1.27 12-04-2018
xcvu160 flgb2104 -1 vu_1_hr_54_by_50_f28 High_Radix 54 50 Fractional 28 Signed 1 NonBlocking Automatic aclk 456 804 1829 16 0 1 PRODUCTION 1.27 12-04-2018
xcvu160 flgb2104 -1 vu_1_hr_54_by_50_f28_lowlat High_Radix 54 50 Fractional 28 Signed 1 NonBlocking Manual 8 aclk 95 748 250 16 0 1 PRODUCTION 1.27 12-04-2018
xcvu160 flgb2104 -1 vu_1_lm LutMult 11 12 Remainder 12 Unsigned 1 NonBlocking Automatic aclk 424 18 127 2 3 0 PRODUCTION 1.27 12-04-2018
xcvu160 flgb2104 -1 vu_1_r2_32_by_32_r32 Radix2 32 32 Remainder 32 Signed 1 NonBlocking Automatic aclk 435 1280 3334 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu160 flgb2104 -1 vu_1_r2_8_by_8_r8 Radix2 8 8 Remainder 8 Signed 1 NonBlocking Automatic aclk 658 124 262 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu160 flgb2104 -1 vu_1_r2_8_by_8_r8_clk2 Radix2 8 8 Remainder 8 Signed 2 NonBlocking Automatic aclk 549 118 207 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu160 flgb2104 -1 vu_1_r2_8_by_8_r8_clk8 Radix2 8 8 Remainder 8 Signed 8 NonBlocking Automatic aclk 577 63 134 0 0 0 PRODUCTION 1.27 12-04-2018

Virtex UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
algorithm_type
dividend_and_quotient_width
divisor_width
remainder_type
fractional_width
operand_sign
clocks_per_division
FlowControl
latency_configuration
latency
Clock Input Fmax (MHz) LUTs FFs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xcvu9p flgb2104 -1 vup_1_hr_10_by_14_f2 High_Radix 10 14 Fractional 2 Signed 1 NonBlocking Manual 17 aclk 571 224 443 7 0 1 PRODUCTION 1.23 03-18-2019
xcvu9p flgb2104 -1 vup_1_hr_36_by_36_f2 High_Radix 36 36 Fractional 2 Signed 1 NonBlocking Automatic aclk 571 545 1208 13 0 1 PRODUCTION 1.23 03-18-2019
xcvu9p flgb2104 -1 vup_1_hr_54_by_50_f28 High_Radix 54 50 Fractional 28 Signed 1 NonBlocking Automatic aclk 566 863 1827 16 0 1 PRODUCTION 1.23 03-18-2019
xcvu9p flgb2104 -1 vup_1_hr_54_by_50_f28_lowlat High_Radix 54 50 Fractional 28 Signed 1 NonBlocking Manual 8 aclk 125 746 250 16 0 1 PRODUCTION 1.23 03-18-2019
xcvu9p flgb2104 -1 vup_1_lm LutMult 11 12 Remainder 12 Unsigned 1 NonBlocking Automatic aclk 631 18 127 2 3 0 PRODUCTION 1.23 03-18-2019
xcvu9p flgb2104 -1 vup_1_r2_32_by_32_r32 Radix2 32 32 Remainder 32 Signed 1 NonBlocking Automatic aclk 713 1279 3334 0 0 0 PRODUCTION 1.23 03-18-2019
xcvu9p flgb2104 -1 vup_1_r2_8_by_8_r8 Radix2 8 8 Remainder 8 Signed 1 NonBlocking Automatic aclk 861 124 262 0 0 0 PRODUCTION 1.23 03-18-2019
xcvu9p flgb2104 -1 vup_1_r2_8_by_8_r8_clk2 Radix2 8 8 Remainder 8 Signed 2 NonBlocking Automatic aclk 790 119 207 0 0 0 PRODUCTION 1.23 03-18-2019
xcvu9p flgb2104 -1 vup_1_r2_8_by_8_r8_clk8 Radix2 8 8 Remainder 8 Signed 8 NonBlocking Automatic aclk 866 62 134 0 0 0 PRODUCTION 1.23 03-18-2019

Zynq UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
algorithm_type
dividend_and_quotient_width
divisor_width
remainder_type
fractional_width
operand_sign
clocks_per_division
FlowControl
latency_configuration
latency
Clock Input Fmax (MHz) LUTs FFs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xczu9eg ffvb1156 -1 zup_1_hr_10_by_14_f2 High_Radix 10 14 Fractional 2 Signed 1 NonBlocking Manual 17 aclk 571 223 443 7 0 1 PRODUCTION 1.25 05-09-2019
xczu9eg ffvb1156 -1 zup_1_hr_36_by_36_f2 High_Radix 36 36 Fractional 2 Signed 1 NonBlocking Automatic aclk 571 542 1208 13 0 1 PRODUCTION 1.25 05-09-2019
xczu9eg ffvb1156 -1 zup_1_hr_54_by_50_f28 High_Radix 54 50 Fractional 28 Signed 1 NonBlocking Automatic aclk 571 862 1827 16 0 1 PRODUCTION 1.25 05-09-2019
xczu9eg ffvb1156 -1 zup_1_hr_54_by_50_f28_lowlat High_Radix 54 50 Fractional 28 Signed 1 NonBlocking Manual 8 aclk 125 750 267 16 0 1 PRODUCTION 1.25 05-09-2019
xczu9eg ffvb1156 -1 zup_1_lm LutMult 11 12 Remainder 12 Unsigned 1 NonBlocking Automatic aclk 625 18 127 2 3 0 PRODUCTION 1.25 05-09-2019
xczu9eg ffvb1156 -1 zup_1_r2_32_by_32_r32 Radix2 32 32 Remainder 32 Signed 1 NonBlocking Automatic aclk 785 1276 3334 0 0 0 PRODUCTION 1.25 05-09-2019
xczu9eg ffvb1156 -1 zup_1_r2_8_by_8_r8 Radix2 8 8 Remainder 8 Signed 1 NonBlocking Automatic aclk 872 125 262 0 0 0 PRODUCTION 1.25 05-09-2019
xczu9eg ffvb1156 -1 zup_1_r2_8_by_8_r8_clk2 Radix2 8 8 Remainder 8 Signed 2 NonBlocking Automatic aclk 790 117 207 0 0 0 PRODUCTION 1.25 05-09-2019
xczu9eg ffvb1156 -1 zup_1_r2_8_by_8_r8_clk8 Radix2 8 8 Remainder 8 Signed 8 NonBlocking Automatic aclk 872 63 134 0 0 0 PRODUCTION 1.25 05-09-2019

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