Performance and Resource Utilization for Reed-Solomon Decoder v9.0

Vivado Design Suite Release 2020.2

Interpreting the results

This page contains maximum frequency and resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Data is provided for the following device families:

Kintex-7

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Code_Specification
Variable_Block_Length
Symbol_Width
Field_Polynomial
Scaling_Factor
Generator_Start
Symbols_Per_Block
Data_Symbols
Number_Of_Supported_R_IN_Values
Number_Of_Channels
erase
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xc7k480t ffg901 -1 k7_1_atsc ATSC false 8 285 1 0 207 187 2 1 false aclk 297 1035 931 0 0 2 PRODUCTION 1.12 2017-02-17
xc7k480t ffg901 -1 k7_1_ccsds CCSDS false 8 391 11 112 255 223 2 1 false aclk 265 1443 1327 0 0 3 PRODUCTION 1.12 2017-02-17
xc7k480t ffg901 -1 k7_1_dvb1 DVB false 8 285 1 0 204 188 2 1 false aclk 281 897 799 0 0 2 PRODUCTION 1.12 2017-02-17
xc7k480t ffg901 -1 k7_1_dvb2 DVB false 8 285 1 0 204 188 2 1 true aclk 275 1932 1389 0 0 2 PRODUCTION 1.12 2017-02-17
xc7k480t ffg901 -1 k7_1_g709 G.709 false 8 285 1 0 255 239 2 1 false aclk 297 774 801 0 0 2 PRODUCTION 1.12 2017-02-17
xc7k480t ffg901 -1 k7_1_g709_2 G.709 false 8 285 1 0 255 239 2 2 false aclk 369 927 1556 0 1 1 PRODUCTION 1.12 2017-02-17
xc7k480t ffg901 -1 k7_1_ieee802_16d IEEE-802.16 true 8 285 1 0 255 239 2 1 false aclk 286 1124 1158 0 1 2 PRODUCTION 1.12 2017-02-17

Kintex UltraScale

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Code_Specification
Variable_Block_Length
Symbol_Width
Field_Polynomial
Scaling_Factor
Generator_Start
Symbols_Per_Block
Data_Symbols
Number_Of_Supported_R_IN_Values
Number_Of_Channels
erase
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcku115 flva1517 -1 ku_1_atsc ATSC false 8 285 1 0 207 187 2 1 false aclk 385 1033 955 0 0 2 PRODUCTION 1.26 12-04-2018
xcku115 flva1517 -1 ku_1_ccsds CCSDS false 8 391 11 112 255 223 2 1 false aclk 336 1431 1351 0 0 3 PRODUCTION 1.26 12-04-2018
xcku115 flva1517 -1 ku_1_dvb1 DVB false 8 285 1 0 204 188 2 1 false aclk 385 900 817 0 0 2 PRODUCTION 1.26 12-04-2018
xcku115 flva1517 -1 ku_1_dvb2 DVB false 8 285 1 0 204 188 2 1 true aclk 358 1873 1413 0 0 2 PRODUCTION 1.26 12-04-2018
xcku115 flva1517 -1 ku_1_g709 G.709 false 8 285 1 0 255 239 2 1 false aclk 380 757 821 0 0 2 PRODUCTION 1.26 12-04-2018
xcku115 flva1517 -1 ku_1_g709_2 G.709 false 8 285 1 0 255 239 2 2 false aclk 424 899 1572 0 1 1 PRODUCTION 1.26 12-04-2018
xcku115 flva1517 -1 ku_1_ieee802_16d IEEE-802.16 true 8 285 1 0 255 239 2 1 false aclk 358 1101 1180 0 1 2 PRODUCTION 1.26 12-04-2018

Kintex UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Code_Specification
Variable_Block_Length
Symbol_Width
Field_Polynomial
Scaling_Factor
Generator_Start
Symbols_Per_Block
Data_Symbols
Number_Of_Supported_R_IN_Values
Number_Of_Channels
erase
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcku13p ffve900 -1 kup_1_atsc ATSC false 8 285 1 0 207 187 2 1 false aclk 527 1023 955 0 0 2 PRODUCTION 1.28 02-27-2020
xcku13p ffve900 -1 kup_1_ccsds CCSDS false 8 391 11 112 255 223 2 1 false aclk 489 1440 1353 0 0 3 PRODUCTION 1.28 02-27-2020
xcku13p ffve900 -1 kup_1_dvb1 DVB false 8 285 1 0 204 188 2 1 false aclk NOT FOUND NOT FOUND
xcku13p ffve900 -1 kup_1_dvb2 DVB false 8 285 1 0 204 188 2 1 true aclk 489 1886 1413 0 0 2 PRODUCTION 1.28 02-27-2020
xcku13p ffve900 -1 kup_1_g709 G.709 false 8 285 1 0 255 239 2 1 false aclk 527 771 825 0 0 2 PRODUCTION 1.28 02-27-2020
xcku13p ffve900 -1 kup_1_g709_2 G.709 false 8 285 1 0 255 239 2 2 false aclk 571 1016 1573 0 1 1 PRODUCTION 1.28 02-27-2020
xcku13p ffve900 -1 kup_1_ieee802_16d IEEE-802.16 true 8 285 1 0 255 239 2 1 false aclk 522 1113 1181 0 1 2 PRODUCTION 1.28 02-27-2020

Versal ACAP

These results are preliminary and based on advanced speedfiles in 2020.2. As production speedfiles are made available and QoR tuning has occurred, the performance will improve. The 2021.1 numbers will be more representative of what can be expected in production.

It is also important to compare the same speedgrade and voltage. These numbers are for low voltage -1 speedgrade VC1902, running at 0.7V. Results from other families are running at higher voltages.

Note that for Versal ACAPs, the performance of the adaptable engines are expected to be similar to the PL performance of 16nm devices. Using the hard IP in Versal enables higher overall system level performance or lower overall power consumption.

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Code_Specification
Variable_Block_Length
Symbol_Width
Field_Polynomial
Scaling_Factor
Generator_Start
Symbols_Per_Block
Data_Symbols
Number_Of_Supported_R_IN_Values
Number_Of_Channels
erase
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcvm1802 vfvc1760 1LP ver_1_atsc ATSC false 8 285 1 0 207 187 2 1 false aclk 413 973 949 0 0 2 ENGINEERING-SAMPLE 1.04 10-18-2020
xcvm1802 vfvc1760 1LP ver_1_ccsds CCSDS false 8 391 11 112 255 223 2 1 false aclk NOT FOUND NOT FOUND
xcvm1802 vfvc1760 1LP ver_1_dvb1 DVB false 8 285 1 0 204 188 2 1 false aclk 407 926 801 0 0 2 ENGINEERING-SAMPLE 1.04 10-18-2020
xcvm1802 vfvc1760 1LP ver_1_dvb2 DVB false 8 285 1 0 204 188 2 1 true aclk 391 1849 1401 0 0 2 ENGINEERING-SAMPLE 1.04 10-18-2020
xcvm1802 vfvc1760 1LP ver_1_g709 G.709 false 8 285 1 0 255 239 2 1 false aclk 413 758 801 0 0 2 ENGINEERING-SAMPLE 1.04 10-18-2020
xcvm1802 vfvc1760 1LP ver_1_g709_2 G.709 false 8 285 1 0 255 239 2 2 false aclk 505 846 1573 0 1 1 ENGINEERING-SAMPLE 1.04 10-18-2020
xcvm1802 vfvc1760 1LP ver_1_ieee802_16d IEEE-802.16 true 8 285 1 0 255 239 2 1 false aclk NOT FOUND NOT FOUND

Virtex-7

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Code_Specification
Variable_Block_Length
Symbol_Width
Field_Polynomial
Scaling_Factor
Generator_Start
Symbols_Per_Block
Data_Symbols
Number_Of_Supported_R_IN_Values
Number_Of_Channels
erase
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xc7vx690t ffg1157 -1 v7_1_atsc ATSC false 8 285 1 0 207 187 2 1 false aclk 286 1038 939 0 0 2 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 v7_1_ccsds CCSDS false 8 391 11 112 255 223 2 1 false aclk 286 1436 1335 0 0 3 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 v7_1_dvb1 DVB false 8 285 1 0 204 188 2 1 false aclk 297 899 807 0 0 2 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 v7_1_dvb2 DVB false 8 285 1 0 204 188 2 1 true aclk 265 1930 1389 0 0 2 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 v7_1_g709 G.709 false 8 285 1 0 255 239 2 1 false aclk 281 771 801 0 0 2 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 v7_1_g709_2 G.709 false 8 285 1 0 255 239 2 2 false aclk 369 927 1556 0 1 1 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 v7_1_ieee802_16d IEEE-802.16 true 8 285 1 0 255 239 2 1 false aclk 265 1116 1157 0 1 2 PRODUCTION 1.11 2014-09-11

Virtex UltraScale

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Code_Specification
Variable_Block_Length
Symbol_Width
Field_Polynomial
Scaling_Factor
Generator_Start
Symbols_Per_Block
Data_Symbols
Number_Of_Supported_R_IN_Values
Number_Of_Channels
erase
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcvu160 flgb2104 -1 vu_1_atsc ATSC false 8 285 1 0 207 187 2 1 false aclk 374 1015 953 0 0 2 PRODUCTION 1.27 12-04-2018
xcvu160 flgb2104 -1 vu_1_ccsds CCSDS false 8 391 11 112 255 223 2 1 false aclk 347 1431 1352 0 0 3 PRODUCTION 1.27 12-04-2018
xcvu160 flgb2104 -1 vu_1_dvb1 DVB false 8 285 1 0 204 188 2 1 false aclk 385 891 817 0 0 2 PRODUCTION 1.27 12-04-2018
xcvu160 flgb2104 -1 vu_1_dvb2 DVB false 8 285 1 0 204 188 2 1 true aclk 336 1879 1413 0 0 2 PRODUCTION 1.27 12-04-2018
xcvu160 flgb2104 -1 vu_1_g709 G.709 false 8 285 1 0 255 239 2 1 false aclk 374 751 819 0 0 2 PRODUCTION 1.27 12-04-2018
xcvu160 flgb2104 -1 vu_1_g709_2 G.709 false 8 285 1 0 255 239 2 2 false aclk 456 913 1573 0 1 1 PRODUCTION 1.27 12-04-2018
xcvu160 flgb2104 -1 vu_1_ieee802_16d IEEE-802.16 true 8 285 1 0 255 239 2 1 false aclk 363 1101 1179 0 1 2 PRODUCTION 1.27 12-04-2018

Virtex UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Code_Specification
Variable_Block_Length
Symbol_Width
Field_Polynomial
Scaling_Factor
Generator_Start
Symbols_Per_Block
Data_Symbols
Number_Of_Supported_R_IN_Values
Number_Of_Channels
erase
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcvu9p flgb2104 -1 vup_1_atsc ATSC false 8 285 1 0 207 187 2 1 false aclk 566 1113 949 0 0 2 PRODUCTION 1.27 02-28-2020
xcvu9p flgb2104 -1 vup_1_ccsds CCSDS false 8 391 11 112 255 223 2 1 false aclk 478 1436 1352 0 0 3 PRODUCTION 1.27 02-28-2020
xcvu9p flgb2104 -1 vup_1_dvb1 DVB false 8 285 1 0 204 188 2 1 false aclk 571 981 818 0 0 2 PRODUCTION 1.27 02-28-2020
xcvu9p flgb2104 -1 vup_1_dvb2 DVB false 8 285 1 0 204 188 2 1 true aclk NOT FOUND NOT FOUND
xcvu9p flgb2104 -1 vup_1_g709 G.709 false 8 285 1 0 255 239 2 1 false aclk 527 766 817 0 0 2 PRODUCTION 1.27 02-28-2020
xcvu9p flgb2104 -1 vup_1_g709_2 G.709 false 8 285 1 0 255 239 2 2 false aclk 571 1021 1573 0 1 1 PRODUCTION 1.27 02-28-2020
xcvu9p flgb2104 -1 vup_1_ieee802_16d IEEE-802.16 true 8 285 1 0 255 239 2 1 false aclk 533 1111 1181 0 1 2 PRODUCTION 1.27 02-28-2020

Zynq UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Code_Specification
Variable_Block_Length
Symbol_Width
Field_Polynomial
Scaling_Factor
Generator_Start
Symbols_Per_Block
Data_Symbols
Number_Of_Supported_R_IN_Values
Number_Of_Channels
erase
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xczu9eg ffvb1156 -1 zup_1_atsc ATSC false 8 285 1 0 207 187 2 1 false aclk 555 1110 955 0 0 2 PRODUCTION 1.29 08-03-2020
xczu9eg ffvb1156 -1 zup_1_ccsds CCSDS false 8 391 11 112 255 223 2 1 false aclk 461 1441 1352 0 0 3 PRODUCTION 1.29 08-03-2020
xczu9eg ffvb1156 -1 zup_1_dvb1 DVB false 8 285 1 0 204 188 2 1 false aclk 566 994 826 0 0 2 PRODUCTION 1.29 08-03-2020
xczu9eg ffvb1156 -1 zup_1_dvb2 DVB false 8 285 1 0 204 188 2 1 true aclk 527 1897 1413 0 0 2 PRODUCTION 1.29 08-03-2020
xczu9eg ffvb1156 -1 zup_1_g709 G.709 false 8 285 1 0 255 239 2 1 false aclk 522 765 825 0 0 2 PRODUCTION 1.29 08-03-2020
xczu9eg ffvb1156 -1 zup_1_g709_2 G.709 false 8 285 1 0 255 239 2 2 false aclk 571 1025 1573 0 1 1 PRODUCTION 1.29 08-03-2020
xczu9eg ffvb1156 -1 zup_1_ieee802_16d IEEE-802.16 true 8 285 1 0 255 239 2 1 false aclk 516 1117 1181 0 1 2 PRODUCTION 1.29 08-03-2020

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