Performance and Resource Utilization for Reed-Solomon Encoder v9.0

Vivado Design Suite Release 2019.2

Interpreting the results

This page contains maximum frequency and resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Data is provided for the following device families:

Kintex-7

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Code_Specification
Variable_Number_Of_Check_Symbols
Variable_Block_Length
Field_Polynomial
Scaling_Factor
Generator_Start
Symbol_Per_Block
Data_Symbols
Check_Symbol_Generator
Number_Of_Channels
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xc7k480t ffg901 -1 k7_1_atsc ATSC false false 285 1 0 207 187 Fixed_Architecture 1 aclk 500 200 213 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k480t ffg901 -1 k7_1_ccsds CCSDS false false 391 11 112 255 223 Fixed_Architecture 1 aclk 265 305 303 0 0 1 PRODUCTION 1.12 2017-02-17
xc7k480t ffg901 -1 k7_1_custom Custom true true 285 1 0 255 239 Optimized_For_Area 1 aclk 265 703 491 0 0 1 PRODUCTION 1.12 2017-02-17
xc7k480t ffg901 -1 k7_1_dvb1 DVB false false 285 1 0 204 188 Fixed_Architecture 1 aclk 516 173 181 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k480t ffg901 -1 k7_1_dvb2 DVB false false 285 1 0 204 188 Fixed_Architecture 16 aclk 478 309 322 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k480t ffg901 -1 k7_1_etsi_bran ETSI_BRAN false true 285 1 0 255 239 Fixed_Architecture 1 aclk 456 193 208 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k480t ffg901 -1 k7_1_g709 G_709 false false 285 1 0 255 239 Fixed_Architecture 1 aclk 522 171 181 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k480t ffg901 -1 k7_1_ituj83 ITU_J_83_Annex_B false false 137 1 1 127 122 Fixed_Architecture 1 aclk 566 85 105 0 0 0 PRODUCTION 1.12 2017-02-17

Kintex UltraScale

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Code_Specification
Variable_Number_Of_Check_Symbols
Variable_Block_Length
Field_Polynomial
Scaling_Factor
Generator_Start
Symbol_Per_Block
Data_Symbols
Check_Symbol_Generator
Number_Of_Channels
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcku115 flva1517 -1 ku_1_atsc ATSC false false 285 1 0 207 187 Fixed_Architecture 1 aclk 664 205 214 0 0 0 PRODUCTION 1.26 12-04-2018
xcku115 flva1517 -1 ku_1_ccsds CCSDS false false 391 11 112 255 223 Fixed_Architecture 1 aclk 347 312 303 0 0 1 PRODUCTION 1.26 12-04-2018
xcku115 flva1517 -1 ku_1_custom Custom true true 285 1 0 255 239 Optimized_For_Area 1 aclk 341 732 491 0 0 1 PRODUCTION 1.26 12-04-2018
xcku115 flva1517 -1 ku_1_dvb1 DVB false false 285 1 0 204 188 Fixed_Architecture 1 aclk 653 177 182 0 0 0 PRODUCTION 1.26 12-04-2018
xcku115 flva1517 -1 ku_1_dvb2 DVB false false 285 1 0 204 188 Fixed_Architecture 16 aclk 615 334 322 0 0 0 PRODUCTION 1.26 12-04-2018
xcku115 flva1517 -1 ku_1_etsi_bran ETSI_BRAN false true 285 1 0 255 239 Fixed_Architecture 1 aclk 599 205 209 0 0 0 PRODUCTION 1.26 12-04-2018
xcku115 flva1517 -1 ku_1_g709 G_709 false false 285 1 0 255 239 Fixed_Architecture 1 aclk 708 178 188 0 0 0 PRODUCTION 1.26 12-04-2018
xcku115 flva1517 -1 ku_1_ituj83 ITU_J_83_Annex_B false false 137 1 1 127 122 Fixed_Architecture 1 aclk 713 84 105 0 0 0 PRODUCTION 1.26 12-04-2018

Kintex UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Code_Specification
Variable_Number_Of_Check_Symbols
Variable_Block_Length
Field_Polynomial
Scaling_Factor
Generator_Start
Symbol_Per_Block
Data_Symbols
Check_Symbol_Generator
Number_Of_Channels
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcku13p ffve900 -1 kup_1_atsc ATSC false false 285 1 0 207 187 Fixed_Architecture 1 aclk 960 205 216 0 0 0 PRODUCTION 1.27 08-13-2019
xcku13p ffve900 -1 kup_1_ccsds CCSDS false false 391 11 112 255 223 Fixed_Architecture 1 aclk 494 313 303 0 0 1 PRODUCTION 1.27 08-13-2019
xcku13p ffve900 -1 kup_1_custom Custom true true 285 1 0 255 239 Optimized_For_Area 1 aclk 478 735 491 0 0 1 PRODUCTION 1.27 08-13-2019
xcku13p ffve900 -1 kup_1_dvb1 DVB false false 285 1 0 204 188 Fixed_Architecture 1 aclk 981 176 193 0 0 0 PRODUCTION 1.27 08-13-2019
xcku13p ffve900 -1 kup_1_dvb2 DVB false false 285 1 0 204 188 Fixed_Architecture 16 aclk 872 335 322 0 0 0 PRODUCTION 1.27 08-13-2019
xcku13p ffve900 -1 kup_1_etsi_bran ETSI_BRAN false true 285 1 0 255 239 Fixed_Architecture 1 aclk 850 203 208 0 0 0 PRODUCTION 1.27 08-13-2019
xcku13p ffve900 -1 kup_1_g709 G_709 false false 285 1 0 255 239 Fixed_Architecture 1 aclk 965 177 183 0 0 0 PRODUCTION 1.27 08-13-2019
xcku13p ffve900 -1 kup_1_ituj83 ITU_J_83_Annex_B false false 137 1 1 127 122 Fixed_Architecture 1 aclk 872 82 105 0 0 0 PRODUCTION 1.27 08-13-2019

Virtex-7

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Code_Specification
Variable_Number_Of_Check_Symbols
Variable_Block_Length
Field_Polynomial
Scaling_Factor
Generator_Start
Symbol_Per_Block
Data_Symbols
Check_Symbol_Generator
Number_Of_Channels
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xc7vx690t ffg1157 -1 v7_1_atsc ATSC false false 285 1 0 207 187 Fixed_Architecture 1 aclk 467 205 213 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 v7_1_ccsds CCSDS false false 391 11 112 255 223 Fixed_Architecture 1 aclk 265 304 303 0 0 1 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 v7_1_custom Custom true true 285 1 0 255 239 Optimized_For_Area 1 aclk 260 701 491 0 0 1 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 v7_1_dvb1 DVB false false 285 1 0 204 188 Fixed_Architecture 1 aclk 467 166 181 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 v7_1_dvb2 DVB false false 285 1 0 204 188 Fixed_Architecture 16 aclk 467 316 322 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 v7_1_etsi_bran ETSI_BRAN false true 285 1 0 255 239 Fixed_Architecture 1 aclk 424 193 208 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 v7_1_g709 G_709 false false 285 1 0 255 239 Fixed_Architecture 1 aclk 467 169 181 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 v7_1_ituj83 ITU_J_83_Annex_B false false 137 1 1 127 122 Fixed_Architecture 1 aclk 577 82 105 0 0 0 PRODUCTION 1.11 2014-09-11

Virtex UltraScale

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Code_Specification
Variable_Number_Of_Check_Symbols
Variable_Block_Length
Field_Polynomial
Scaling_Factor
Generator_Start
Symbol_Per_Block
Data_Symbols
Check_Symbol_Generator
Number_Of_Channels
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcvu160 flgb2104 -1 vu_1_atsc ATSC false false 285 1 0 207 187 Fixed_Architecture 1 aclk 664 204 213 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu160 flgb2104 -1 vu_1_ccsds CCSDS false false 391 11 112 255 223 Fixed_Architecture 1 aclk 341 317 303 0 0 1 PRODUCTION 1.27 12-04-2018
xcvu160 flgb2104 -1 vu_1_custom Custom true true 285 1 0 255 239 Optimized_For_Area 1 aclk 336 734 491 0 0 1 PRODUCTION 1.27 12-04-2018
xcvu160 flgb2104 -1 vu_1_dvb1 DVB false false 285 1 0 204 188 Fixed_Architecture 1 aclk 669 179 182 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu160 flgb2104 -1 vu_1_dvb2 DVB false false 285 1 0 204 188 Fixed_Architecture 16 aclk 647 329 322 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu160 flgb2104 -1 vu_1_etsi_bran ETSI_BRAN false true 285 1 0 255 239 Fixed_Architecture 1 aclk 571 200 208 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu160 flgb2104 -1 vu_1_g709 G_709 false false 285 1 0 255 239 Fixed_Architecture 1 aclk 647 176 185 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu160 flgb2104 -1 vu_1_ituj83 ITU_J_83_Annex_B false false 137 1 1 127 122 Fixed_Architecture 1 aclk 735 87 105 0 0 0 PRODUCTION 1.27 12-04-2018

Virtex UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Code_Specification
Variable_Number_Of_Check_Symbols
Variable_Block_Length
Field_Polynomial
Scaling_Factor
Generator_Start
Symbol_Per_Block
Data_Symbols
Check_Symbol_Generator
Number_Of_Channels
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcvu9p flgb2104 -1 vup_1_atsc ATSC false false 285 1 0 207 187 Fixed_Architecture 1 aclk 905 205 213 0 0 0 PRODUCTION 1.26 08-13-2019
xcvu9p flgb2104 -1 vup_1_ccsds CCSDS false false 391 11 112 255 223 Fixed_Architecture 1 aclk 478 307 303 0 0 1 PRODUCTION 1.26 08-13-2019
xcvu9p flgb2104 -1 vup_1_custom Custom true true 285 1 0 255 239 Optimized_For_Area 1 aclk 472 728 491 0 0 1 PRODUCTION 1.26 08-13-2019
xcvu9p flgb2104 -1 vup_1_dvb1 DVB false false 285 1 0 204 188 Fixed_Architecture 1 aclk 921 177 186 0 0 0 PRODUCTION 1.26 08-13-2019
xcvu9p flgb2104 -1 vup_1_dvb2 DVB false false 285 1 0 204 188 Fixed_Architecture 16 aclk 866 330 322 0 0 0 PRODUCTION 1.26 08-13-2019
xcvu9p flgb2104 -1 vup_1_etsi_bran ETSI_BRAN false true 285 1 0 255 239 Fixed_Architecture 1 aclk 861 204 208 0 0 0 PRODUCTION 1.26 08-13-2019
xcvu9p flgb2104 -1 vup_1_g709 G_709 false false 285 1 0 255 239 Fixed_Architecture 1 aclk 1019 175 181 0 0 0 PRODUCTION 1.26 08-13-2019
xcvu9p flgb2104 -1 vup_1_ituj83 ITU_J_83_Annex_B false false 137 1 1 127 122 Fixed_Architecture 1 aclk 872 82 105 0 0 0 PRODUCTION 1.26 08-13-2019

Zynq UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
Code_Specification
Variable_Number_Of_Check_Symbols
Variable_Block_Length
Field_Polynomial
Scaling_Factor
Generator_Start
Symbol_Per_Block
Data_Symbols
Check_Symbol_Generator
Number_Of_Channels
Clock Input Fmax (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xczu9eg ffvb1156 -1 zup_1_atsc ATSC false false 285 1 0 207 187 Fixed_Architecture 1 aclk 975 210 216 0 0 0 PRODUCTION 1.26 08-13-2019
xczu9eg ffvb1156 -1 zup_1_ccsds CCSDS false false 391 11 112 255 223 Fixed_Architecture 1 aclk 478 303 303 0 0 1 PRODUCTION 1.26 08-13-2019
xczu9eg ffvb1156 -1 zup_1_custom Custom true true 285 1 0 255 239 Optimized_For_Area 1 aclk 489 728 491 0 0 1 PRODUCTION 1.26 08-13-2019
xczu9eg ffvb1156 -1 zup_1_dvb1 DVB false false 285 1 0 204 188 Fixed_Architecture 1 aclk 938 174 181 0 0 0 PRODUCTION 1.26 08-13-2019
xczu9eg ffvb1156 -1 zup_1_dvb2 DVB false false 285 1 0 204 188 Fixed_Architecture 16 aclk 866 332 324 0 0 0 PRODUCTION 1.26 08-13-2019
xczu9eg ffvb1156 -1 zup_1_etsi_bran ETSI_BRAN false true 285 1 0 255 239 Fixed_Architecture 1 aclk 861 204 209 0 0 0 PRODUCTION 1.26 08-13-2019
xczu9eg ffvb1156 -1 zup_1_g709 G_709 false false 285 1 0 255 239 Fixed_Architecture 1 aclk 938 176 181 0 0 0 PRODUCTION 1.26 08-13-2019
xczu9eg ffvb1156 -1 zup_1_ituj83 ITU_J_83_Annex_B false false 137 1 1 127 122 Fixed_Architecture 1 aclk 872 81 105 0 0 0 PRODUCTION 1.26 08-13-2019

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