Performance and Resource Utilization for Video Frame Buffer Read v1.0

Vivado Design Suite Release 2017.1

Interpreting the results

This page contains maximum frequency and resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Zynq UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
SAMPLES_PER_CLOCK
MAX_COLS
MAX_ROWS
MAX_DATA_WIDTH
AXIMM_DATA_WIDTH
HAS_RGBX8
HAS_YUVX8
HAS_YUYV8
HAS_RGBX10
HAS_YUVX10
HAS_Y_UV8
HAS_Y_UV8_420
HAS_RGB8
HAS_YUV8
HAS_Y_UV10
HAS_Y_UV10_420
HAS_Y8
HAS_Y10
MAX_NR_PLANES
Clock Input Fmax (MHz) LUTs FFs LUT-FF Pairs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xczu9eg ffvb1156 -1 v_frmbuf_rd_08bit__conf_28 1 3840 2160 8 64 1 0 0 0 0 0 0 0 0 0 0 0 0 1 ap_clk 538 1462 1978 825 1 3 0 PRODUCTION 1.09 03-16-2017
xczu9eg ffvb1156 -1 v_frmbuf_rd_08bit__conf_29 2 3840 2160 8 128 1 0 0 0 0 0 0 0 0 0 0 0 0 1 ap_clk 519 1774 2597 1084 1 4 0 PRODUCTION 1.09 03-16-2017
xczu9eg ffvb1156 -1 v_frmbuf_rd_08bit__conf_30 4 3840 2160 8 256 1 0 0 0 0 0 0 0 0 0 0 0 0 1 ap_clk 500 2558 3855 1578 1 8 0 PRODUCTION 1.09 03-16-2017
xczu9eg ffvb1156 -1 v_frmbuf_rd_08bit__conf_31 1 3840 2160 8 64 0 0 1 0 0 0 0 0 0 0 0 0 0 1 ap_clk 494 1478 2025 868 1 3 0 PRODUCTION 1.09 03-16-2017
xczu9eg ffvb1156 -1 v_frmbuf_rd_08bit__conf_32 2 3840 2160 8 128 0 0 1 0 0 0 0 0 0 0 0 0 0 1 ap_clk 513 1801 2685 1084 1 4 0 PRODUCTION 1.09 03-16-2017
xczu9eg ffvb1156 -1 v_frmbuf_rd_08bit__conf_33 4 3840 2160 8 256 0 0 1 0 0 0 0 0 0 0 0 0 0 1 ap_clk 507 2532 4024 1610 1 8 0 PRODUCTION 1.09 03-16-2017
xczu9eg ffvb1156 -1 v_frmbuf_rd_08bit__conf_34 1 3840 2160 8 64 0 0 0 0 0 1 0 0 0 0 0 0 0 2 ap_clk 519 1841 2694 1094 2 5 0 PRODUCTION 1.09 03-16-2017
xczu9eg ffvb1156 -1 v_frmbuf_rd_08bit__conf_35 2 3840 2160 8 128 0 0 0 0 0 1 0 0 0 0 0 0 0 2 ap_clk 494 2279 3598 1416 2 6 0 PRODUCTION 1.09 03-16-2017
xczu9eg ffvb1156 -1 v_frmbuf_rd_08bit__conf_36 4 3840 2160 8 256 0 0 0 0 0 1 0 0 0 0 0 0 0 2 ap_clk 469 3145 5455 2094 2 12 0 PRODUCTION 1.09 03-16-2017
xczu9eg ffvb1156 -1 v_frmbuf_rd_08bit__conf_37 1 3840 2160 8 64 0 0 0 0 0 0 0 1 0 0 0 0 0 1 ap_clk 507 1595 2132 855 2 3 0 PRODUCTION 1.09 03-16-2017
xczu9eg ffvb1156 -1 v_frmbuf_rd_08bit__conf_38 2 3840 2160 8 128 0 0 0 0 0 0 0 1 0 0 0 0 0 1 ap_clk 500 2000 2923 1138 2 4 0 PRODUCTION 1.09 03-16-2017
xczu9eg ffvb1156 -1 v_frmbuf_rd_08bit__conf_39 4 3840 2160 8 256 0 0 0 0 0 0 0 1 0 0 0 0 0 1 ap_clk 444 2970 4530 1607 2 8 0 PRODUCTION 1.09 03-16-2017
xczu9eg ffvb1156 -1 v_frmbuf_rd_08bit__conf_40 1 3840 2160 8 64 0 0 0 0 0 0 0 0 0 0 0 1 0 1 ap_clk 519 1477 2029 839 1 3 0 PRODUCTION 1.09 03-16-2017
xczu9eg ffvb1156 -1 v_frmbuf_rd_08bit__conf_41 2 3840 2160 8 128 0 0 0 0 0 0 0 0 0 0 0 1 0 1 ap_clk 525 1751 2681 1063 1 4 0 PRODUCTION 1.09 03-16-2017
xczu9eg ffvb1156 -1 v_frmbuf_rd_08bit__conf_42 4 3840 2160 8 256 0 0 0 0 0 0 0 0 0 0 0 1 0 1 ap_clk 513 2398 4005 1581 1 8 0 PRODUCTION 1.09 03-16-2017
xczu9eg ffvb1156 -1 v_frmbuf_rd_08bit__conf_43 1 3840 2160 8 64 1 1 1 0 0 1 1 1 1 0 0 1 0 2 ap_clk 469 2375 3206 1198 3 5 0 PRODUCTION 1.09 03-16-2017
xczu9eg ffvb1156 -1 v_frmbuf_rd_08bit__conf_44 2 3840 2160 8 128 1 1 1 0 0 1 1 1 1 0 0 1 0 2 ap_clk 419 2877 4250 1497 3 6 0 PRODUCTION 1.09 03-16-2017
xczu9eg ffvb1156 -1 v_frmbuf_rd_08bit__conf_45 4 3840 2160 8 256 1 1 1 0 0 1 1 1 1 0 0 1 0 2 ap_clk 394 4307 6411 2158 3 12 0 PRODUCTION 1.09 03-16-2017
xczu9eg ffvb1156 -1 v_frmbuf_rd_10bit__conf_01 1 3840 2160 10 64 1 0 0 0 0 0 0 0 0 0 0 0 0 1 ap_clk 525 1472 1978 848 1 3 0 PRODUCTION 1.09 03-16-2017
xczu9eg ffvb1156 -1 v_frmbuf_rd_10bit__conf_02 2 3840 2160 10 128 1 0 0 0 0 0 0 0 0 0 0 0 0 1 ap_clk 519 1774 2597 1074 1 4 0 PRODUCTION 1.09 03-16-2017
xczu9eg ffvb1156 -1 v_frmbuf_rd_10bit__conf_03 4 3840 2160 10 256 1 0 0 0 0 0 0 0 0 0 0 0 0 1 ap_clk 550 2567 3855 1550 1 8 0 PRODUCTION 1.09 03-16-2017
xczu9eg ffvb1156 -1 v_frmbuf_rd_10bit__conf_04 1 3840 2160 10 64 0 0 1 0 0 0 0 0 0 0 0 0 0 1 ap_clk 550 1481 2025 860 1 3 0 PRODUCTION 1.09 03-16-2017
xczu9eg ffvb1156 -1 v_frmbuf_rd_10bit__conf_05 2 3840 2160 10 128 0 0 1 0 0 0 0 0 0 0 0 0 0 1 ap_clk 550 1806 2685 1092 1 4 0 PRODUCTION 1.09 03-16-2017
xczu9eg ffvb1156 -1 v_frmbuf_rd_10bit__conf_06 4 3840 2160 10 256 0 0 1 0 0 0 0 0 0 0 0 0 0 1 ap_clk 513 2543 4024 1633 1 8 0 PRODUCTION 1.09 03-16-2017
xczu9eg ffvb1156 -1 v_frmbuf_rd_10bit__conf_07 1 3840 2160 10 64 0 0 0 1 0 0 0 0 0 0 0 0 0 1 ap_clk 519 1522 2032 863 1 3 0 PRODUCTION 1.09 03-16-2017
xczu9eg ffvb1156 -1 v_frmbuf_rd_10bit__conf_08 2 3840 2160 10 128 0 0 0 1 0 0 0 0 0 0 0 0 0 1 ap_clk 507 1842 2705 1124 1 4 0 PRODUCTION 1.09 03-16-2017
xczu9eg ffvb1156 -1 v_frmbuf_rd_10bit__conf_09 4 3840 2160 10 256 0 0 0 1 0 0 0 0 0 0 0 0 0 1 ap_clk 500 2764 4071 1684 1 8 0 PRODUCTION 1.09 03-16-2017
xczu9eg ffvb1156 -1 v_frmbuf_rd_10bit__conf_10 1 3840 2160 10 64 0 0 0 0 0 1 0 0 0 0 0 0 0 2 ap_clk 525 1845 2694 1082 2 5 0 PRODUCTION 1.09 03-16-2017
xczu9eg ffvb1156 -1 v_frmbuf_rd_10bit__conf_11 2 3840 2160 10 128 0 0 0 0 0 1 0 0 0 0 0 0 0 2 ap_clk 538 2272 3598 1443 2 6 0 PRODUCTION 1.09 03-16-2017
xczu9eg ffvb1156 -1 v_frmbuf_rd_10bit__conf_12 4 3840 2160 10 256 0 0 0 0 0 1 0 0 0 0 0 0 0 2 ap_clk 432 3151 5455 2081 2 12 0 PRODUCTION 1.09 03-16-2017
xczu9eg ffvb1156 -1 v_frmbuf_rd_10bit__conf_13 1 3840 2160 10 64 0 0 0 0 0 0 0 1 0 0 0 0 0 1 ap_clk 513 1619 2132 862 2 3 0 PRODUCTION 1.09 03-16-2017
xczu9eg ffvb1156 -1 v_frmbuf_rd_10bit__conf_14 2 3840 2160 10 128 0 0 0 0 0 0 0 1 0 0 0 0 0 1 ap_clk 494 2002 2923 1126 2 4 0 PRODUCTION 1.09 03-16-2017
xczu9eg ffvb1156 -1 v_frmbuf_rd_10bit__conf_15 4 3840 2160 10 256 0 0 0 0 0 0 0 1 0 0 0 0 0 1 ap_clk 457 3001 4530 1657 2 8 0 PRODUCTION 1.09 03-16-2017
xczu9eg ffvb1156 -1 v_frmbuf_rd_10bit__conf_16 1 3840 2160 10 64 0 0 0 0 0 0 0 0 0 1 0 0 0 2 ap_clk 519 1849 2601 1078 2 5 0 PRODUCTION 1.09 03-16-2017
xczu9eg ffvb1156 -1 v_frmbuf_rd_10bit__conf_17 2 3840 2160 10 128 0 0 0 0 0 0 0 0 0 1 0 0 0 2 ap_clk 513 2296 3497 1389 2 6 0 PRODUCTION 1.09 03-16-2017
xczu9eg ffvb1156 -1 v_frmbuf_rd_10bit__conf_18 4 3840 2160 10 256 0 0 0 0 0 0 0 0 0 1 0 0 0 2 ap_clk 463 3261 5318 2081 2 12 0 PRODUCTION 1.09 03-16-2017
xczu9eg ffvb1156 -1 v_frmbuf_rd_10bit__conf_19 1 3840 2160 10 64 0 0 0 0 0 0 0 0 0 0 0 1 0 1 ap_clk 550 1480 2029 827 1 3 0 PRODUCTION 1.09 03-16-2017
xczu9eg ffvb1156 -1 v_frmbuf_rd_10bit__conf_20 2 3840 2160 10 128 0 0 0 0 0 0 0 0 0 0 0 1 0 1 ap_clk 519 1749 2681 1047 1 4 0 PRODUCTION 1.09 03-16-2017
xczu9eg ffvb1156 -1 v_frmbuf_rd_10bit__conf_21 4 3840 2160 10 256 0 0 0 0 0 0 0 0 0 0 0 1 0 1 ap_clk 513 2405 4005 1582 1 8 0 PRODUCTION 1.09 03-16-2017
xczu9eg ffvb1156 -1 v_frmbuf_rd_10bit__conf_22 1 3840 2160 10 64 0 0 0 0 0 0 0 0 0 0 0 0 1 1 ap_clk 532 1533 1997 883 1 3 0 PRODUCTION 1.09 03-16-2017
xczu9eg ffvb1156 -1 v_frmbuf_rd_10bit__conf_23 2 3840 2160 10 128 0 0 0 0 0 0 0 0 0 0 0 0 1 1 ap_clk 538 1826 2651 1087 1 4 0 PRODUCTION 1.09 03-16-2017
xczu9eg ffvb1156 -1 v_frmbuf_rd_10bit__conf_24 4 3840 2160 10 256 0 0 0 0 0 0 0 0 0 0 0 0 1 1 ap_clk 469 2462 3980 1598 1 8 0 PRODUCTION 1.09 03-16-2017
xczu9eg ffvb1156 -1 v_frmbuf_rd_10bit__conf_25 1 3840 2160 10 64 1 1 1 1 1 1 1 1 1 1 1 1 1 2 ap_clk 413 2844 3827 1312 3 5 0 PRODUCTION 1.09 03-16-2017
xczu9eg ffvb1156 -1 v_frmbuf_rd_10bit__conf_26 2 3840 2160 10 128 1 1 1 1 1 1 1 1 1 1 1 1 1 2 ap_clk 400 3658 5039 1707 3 6 0 PRODUCTION 1.09 03-16-2017
xczu9eg ffvb1156 -1 v_frmbuf_rd_10bit__conf_27 4 3840 2160 10 256 1 1 1 1 1 1 1 1 1 1 1 1 1 2 ap_clk 319 5345 7591 2452 3 12 0 PRODUCTION 1.09 03-16-2017

COPYRIGHT

Copyright 2017 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners.

LEGAL INFORMATION: PLEASE READ

The information disclosed to you hereunder (the "Materials") is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to product specifications. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are subject to the terms and conditions of Xilinx's limited warranty, please refer to Xilinx's Terms of Sale which can be viewed at https://www.xilinx.com/legal.htm#tos; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in such critical applications, please refer to Xilinx's Terms of Sale which can be viewed at https://www.xilinx.com/legal.htm#tos.