Performance and Resource Utilization for DSP48 Macro v3.0

Vivado Design Suite Release 2017.3

Interpreting the results

This page contains maximum frequency and resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Data is provided for the following device families:

Kintex-7

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
instruction1
instruction2
instruction3
instruction4
pipeline_options
tier_5
tier_6
output_properties
p_width
Clock Input Fmax (MHz) LUTs FFs LUT-FF Pairs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xc7k480t ffg901 -1 k7_1_1 C C+P C-P CLK 548 2 108 2 1 0 0 PRODUCTION 1.12 2017-02-17
xc7k480t ffg901 -1 k7_1_2 C+CONCAT+PCIN By_Tier true true CLK 548 0 0 0 1 0 0 PRODUCTION 1.12 2017-02-17
xc7k480t ffg901 -1 k7_1_3 C+CONCAT By_Tier true true CLK 548 0 0 0 1 0 0 PRODUCTION 1.12 2017-02-17
xc7k480t ffg901 -1 k7_1_4 A*B P+A*B CLK 548 1 10 1 1 0 0 PRODUCTION 1.12 2017-02-17
xc7k480t ffg901 -1 k7_1_5 (A+D)*B (A+D)*B+P A*B+P RNDSIMPLE(P) User_Defined 18 CLK 548 3 42 2 1 0 0 PRODUCTION 1.12 2017-02-17
xc7k480t ffg901 -1 k7_1_6 A*B A*B+P RNDSIMPLE(P) User_Defined 18 CLK 548 3 42 3 1 0 0 PRODUCTION 1.12 2017-02-17

Kintex UltraScale

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
instruction1
instruction2
instruction3
instruction4
pipeline_options
tier_5
tier_6
output_properties
p_width
Clock Input Fmax (MHz) LUTs FFs LUT-FF Pairs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xcku115 flva1517 -1 ku_1_1 C C+P C-P CLK 625 2 106 1 1 0 0 PRODUCTION 1.24 03-22-2017
xcku115 flva1517 -1 ku_1_2 C+CONCAT+PCIN By_Tier true true CLK 735 0 0 0 1 0 0 PRODUCTION 1.24 03-22-2017
xcku115 flva1517 -1 ku_1_3 C+CONCAT By_Tier true true CLK 735 0 0 0 1 0 0 PRODUCTION 1.24 03-22-2017
xcku115 flva1517 -1 ku_1_4 A*B P+A*B CLK 625 0 10 0 1 0 0 PRODUCTION 1.24 03-22-2017
xcku115 flva1517 -1 ku_1_5 (A+D)*B (A+D)*B+P A*B+P RNDSIMPLE(P) User_Defined 18 CLK 625 2 14 1 1 0 0 PRODUCTION 1.24 03-22-2017
xcku115 flva1517 -1 ku_1_6 A*B A*B+P RNDSIMPLE(P) User_Defined 18 CLK 625 2 14 0 1 0 0 PRODUCTION 1.24 03-22-2017

Kintex UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
instruction1
instruction2
instruction3
instruction4
pipeline_options
tier_5
tier_6
output_properties
p_width
Clock Input Fmax (MHz) LUTs FFs LUT-FF Pairs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xcku13p ffve900 -1 kup_1_1 C C+P C-P CLK 829 2 106 1 1 0 0 PRODUCTION 1.14 09-15-2017
xcku13p ffve900 -1 kup_1_2 C+CONCAT+PCIN By_Tier true true CLK 1329 0 0 0 1 0 0 PRODUCTION 1.14 09-15-2017
xcku13p ffve900 -1 kup_1_3 C+CONCAT By_Tier true true CLK 1329 0 0 0 1 0 0 PRODUCTION 1.14 09-15-2017
xcku13p ffve900 -1 kup_1_4 A*B P+A*B CLK 829 0 10 0 1 0 0 PRODUCTION 1.14 09-15-2017
xcku13p ffve900 -1 kup_1_5 (A+D)*B (A+D)*B+P A*B+P RNDSIMPLE(P) User_Defined 18 CLK 829 2 14 1 1 0 0 PRODUCTION 1.14 09-15-2017
xcku13p ffve900 -1 kup_1_6 A*B A*B+P RNDSIMPLE(P) User_Defined 18 CLK 829 2 14 0 1 0 0 PRODUCTION 1.14 09-15-2017

Virtex-7

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
instruction1
instruction2
instruction3
instruction4
pipeline_options
tier_5
tier_6
output_properties
p_width
Clock Input Fmax (MHz) LUTs FFs LUT-FF Pairs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xc7vx690t ffg1157 -1 v7_1_1 C C+P C-P CLK 548 2 108 2 1 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 v7_1_2 C+CONCAT+PCIN By_Tier true true CLK 548 0 0 0 1 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 v7_1_3 C+CONCAT By_Tier true true CLK 548 0 0 0 1 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 v7_1_4 A*B P+A*B CLK 548 1 10 1 1 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 v7_1_5 (A+D)*B (A+D)*B+P A*B+P RNDSIMPLE(P) User_Defined 18 CLK 548 3 42 2 1 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 v7_1_6 A*B A*B+P RNDSIMPLE(P) User_Defined 18 CLK 548 3 42 1 1 0 0 PRODUCTION 1.11 2014-09-11

Virtex UltraScale

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
instruction1
instruction2
instruction3
instruction4
pipeline_options
tier_5
tier_6
output_properties
p_width
Clock Input Fmax (MHz) LUTs FFs LUT-FF Pairs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xcvu160 flgb2104 -1 vu_1_1 C C+P C-P CLK 625 2 106 1 1 0 0 PRODUCTION 1.25 03-22-2017
xcvu160 flgb2104 -1 vu_1_2 C+CONCAT+PCIN By_Tier true true CLK 735 0 0 0 1 0 0 PRODUCTION 1.25 03-22-2017
xcvu160 flgb2104 -1 vu_1_3 C+CONCAT By_Tier true true CLK 735 0 0 0 1 0 0 PRODUCTION 1.25 03-22-2017
xcvu160 flgb2104 -1 vu_1_4 A*B P+A*B CLK 625 0 10 0 1 0 0 PRODUCTION 1.25 03-22-2017
xcvu160 flgb2104 -1 vu_1_5 (A+D)*B (A+D)*B+P A*B+P RNDSIMPLE(P) User_Defined 18 CLK 625 2 14 1 1 0 0 PRODUCTION 1.25 03-22-2017
xcvu160 flgb2104 -1 vu_1_6 A*B A*B+P RNDSIMPLE(P) User_Defined 18 CLK 625 2 14 0 1 0 0 PRODUCTION 1.25 03-22-2017

Virtex UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
instruction1
instruction2
instruction3
instruction4
pipeline_options
tier_5
tier_6
output_properties
p_width
Clock Input Fmax (MHz) LUTs FFs LUT-FF Pairs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xcvu9p flgb2104 -1 vup_1_1 C C+P C-P CLK 829 2 106 1 1 0 0 PRODUCTION 1.14 09-15-2017
xcvu9p flgb2104 -1 vup_1_2 C+CONCAT+PCIN By_Tier true true CLK 1329 0 0 0 1 0 0 PRODUCTION 1.14 09-15-2017
xcvu9p flgb2104 -1 vup_1_3 C+CONCAT By_Tier true true CLK 1329 0 0 0 1 0 0 PRODUCTION 1.14 09-15-2017
xcvu9p flgb2104 -1 vup_1_4 A*B P+A*B CLK 829 0 10 0 1 0 0 PRODUCTION 1.14 09-15-2017
xcvu9p flgb2104 -1 vup_1_5 (A+D)*B (A+D)*B+P A*B+P RNDSIMPLE(P) User_Defined 18 CLK 829 2 14 1 1 0 0 PRODUCTION 1.14 09-15-2017
xcvu9p flgb2104 -1 vup_1_6 A*B A*B+P RNDSIMPLE(P) User_Defined 18 CLK 829 2 14 0 1 0 0 PRODUCTION 1.14 09-15-2017

Zynq UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
instruction1
instruction2
instruction3
instruction4
pipeline_options
tier_5
tier_6
output_properties
p_width
Clock Input Fmax (MHz) LUTs FFs LUT-FF Pairs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xczu9eg ffvb1156 -1 zup_1_1 C C+P C-P CLK 829 2 106 1 1 0 0 PRODUCTION 1.15 10-03-2017
xczu9eg ffvb1156 -1 zup_1_2 C+CONCAT+PCIN By_Tier true true CLK 1329 0 0 0 1 0 0 PRODUCTION 1.15 10-03-2017
xczu9eg ffvb1156 -1 zup_1_3 C+CONCAT By_Tier true true CLK 1329 0 0 0 1 0 0 PRODUCTION 1.15 10-03-2017
xczu9eg ffvb1156 -1 zup_1_4 A*B P+A*B CLK 829 0 10 0 1 0 0 PRODUCTION 1.15 10-03-2017
xczu9eg ffvb1156 -1 zup_1_5 (A+D)*B (A+D)*B+P A*B+P RNDSIMPLE(P) User_Defined 18 CLK 829 2 14 1 1 0 0 PRODUCTION 1.15 10-03-2017
xczu9eg ffvb1156 -1 zup_1_6 A*B A*B+P RNDSIMPLE(P) User_Defined 18 CLK 829 2 14 0 1 0 0 PRODUCTION 1.15 10-03-2017

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