Resource Utilization for DMA/Bridge Subsystem for PCI Express (PCIe) v4.0

Vivado Design Suite Release 2017.3

Interpreting the results

This page contains resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Data is provided for the following device families:

Virtex-7

Part Information Configuration Parameters Resource Utilization
Device Package Speed Grade Configuration Name
functional_mode
device_port_type
pl_link_cap_max_link_width
pl_link_cap_max_link_speed
axi_data_width
en_axi_slave_if
en_axi_master_if
xdma_rnum_chnl
xdma_wnum_chnl
xdma_rnum_rids
xdma_wnum_rids
xdma_axi_intf_mm
en_axi_slave_if
en_axi_master_if
c_m_axi_num_write
c_s_axi_num_write
Fixed clocks (MHz) LUTs FFs LUT-FF Pairs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xc7vx690t ffg1761 -3 fcsvrg1x8_chnl1_64bit X1 8.0_GT/s 64_bit 1 1 DUT/inst/pcie3_ip_i/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gth_channel.gthe2_channel_i/TXOUTCLK=100 axi_aclk=125 sys_clk=100 11551 12347 5709 0 14 12 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1761 -3 fcsvrg1x8_chnl4_64bit X1 8.0_GT/s 64_bit 4 4 64 32 DUT/inst/pcie3_ip_i/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gth_channel.gthe2_channel_i/TXOUTCLK=100 axi_aclk=125 sys_clk=100 28727 28850 13139 0 26 12 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1761 -3 fcsvrg2x8_chnl1_128bit X8 5.0_GT/s 128_bit 1 1 DUT/inst/pcie3_ip_i/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gth_channel.gthe2_channel_i/TXOUTCLK=100 axi_aclk=250 sys_clk=100 17401 17199 8221 0 25 4 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1761 -3 fcsvrg3x8_chnl1_256bit X8 8.0_GT/s 256_bit 1 1 DUT/inst/pcie3_ip_i/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gth_channel.gthe2_channel_i/TXOUTCLK=100 axi_aclk=250 sys_clk=100 24601 21021 10162 0 33 12 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1761 -3 fcsvrg3x8_chnl4_256bit X8 8.0_GT/s 256_bit 4 4 64 32 DUT/inst/pcie3_ip_i/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gth_channel.gthe2_channel_i/TXOUTCLK=100 axi_aclk=250 sys_clk=100 43162 37587 18497 0 63 12 PRODUCTION 1.11 2014-09-11

Virtex UltraScale

Part Information Configuration Parameters Resource Utilization
Device Package Speed Grade Configuration Name
functional_mode
device_port_type
pl_link_cap_max_link_width
pl_link_cap_max_link_speed
axi_data_width
en_axi_slave_if
en_axi_master_if
xdma_rnum_chnl
xdma_wnum_chnl
xdma_rnum_rids
xdma_wnum_rids
xdma_axi_intf_mm
en_axi_slave_if
en_axi_master_if
c_m_axi_num_write
c_s_axi_num_write
Fixed clocks (MHz) LUTs FFs LUT-FF Pairs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xcvu095 ffva2104 -3 xcvu095g1x1_chnl1_mm X1 2.5_GT/s 1 1 AXI_Memory_Mapped axi_aclk=62 sys_clk=100 sys_clk_gt=100 11011 12165 5261 0 14 12 PRODUCTION 1.24 03-22-2017
xcvu095 ffva2104 -3 xcvu095g1x1_chnl1_stream X1 2.5_GT/s 1 1 AXI_Stream axi_aclk=62 sys_clk=100 sys_clk_gt=100 9969 10811 4708 0 15 12 PRODUCTION 1.24 03-22-2017
xcvu095 ffva2104 -3 xcvu095g1x1_chnl4_mm X1 2.5_GT/s 4 4 AXI_Memory_Mapped axi_aclk=62 sys_clk=100 sys_clk_gt=100 25934 27161 11713 0 26 12 PRODUCTION 1.24 03-22-2017
xcvu095 ffva2104 -3 xcvu095g1x1_chnl4_stream X1 2.5_GT/s 4 4 AXI_Stream axi_aclk=62 sys_clk=100 sys_clk_gt=100 25711 25151 11034 0 30 12 PRODUCTION 1.24 03-22-2017
xcvu095 ffva2104 -3 xcvu095g3x8_chnl1_mm X8 8.0_GT/s 1 1 AXI_Memory_Mapped axi_aclk=250 sys_clk=100 sys_clk_gt=100 21033 19986 8636 0 33 12 PRODUCTION 1.24 03-22-2017
xcvu095 ffva2104 -3 xcvu095g3x8_chnl1_stream X8 8.0_GT/s 1 1 AXI_Stream axi_aclk=250 sys_clk=100 sys_clk_gt=100 18844 18651 7823 0 34 12 PRODUCTION 1.24 03-22-2017
xcvu095 ffva2104 -3 xcvu095g3x8_chnl4_mm X8 8.0_GT/s 4 4 AXI_Memory_Mapped axi_aclk=250 sys_clk=100 sys_clk_gt=100 37085 35032 15472 0 63 12 PRODUCTION 1.24 03-22-2017
xcvu095 ffva2104 -3 xcvu095g3x8_chnl4_stream X8 8.0_GT/s 4 4 AXI_Stream axi_aclk=250 sys_clk=100 sys_clk_gt=100 40411 36838 15307 0 67 12 PRODUCTION 1.24 03-22-2017

Virtex UltraScale+

Part Information Configuration Parameters Resource Utilization
Device Package Speed Grade Configuration Name
functional_mode
device_port_type
pl_link_cap_max_link_width
pl_link_cap_max_link_speed
axi_data_width
en_axi_slave_if
en_axi_master_if
xdma_rnum_chnl
xdma_wnum_chnl
xdma_rnum_rids
xdma_wnum_rids
xdma_axi_intf_mm
en_axi_slave_if
en_axi_master_if
c_m_axi_num_write
c_s_axi_num_write
Fixed clocks (MHz) LUTs FFs LUT-FF Pairs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x16g3_MS_16_ep_bridge AXI_Bridge PCI_Express_Endpoint_device X16 8.0_GT/s 512_bit true true true true 16 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=500 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[10].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[11].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[12].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[13].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[14].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[15].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[4].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[5].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[6].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[7].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[8].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[9].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=250 sys_clk=100 sys_clk_gt=100 45269 45214 17295 0 64 0 ADVANCE 1.14 09-15-2017
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x16g3_MS_16_rp_bridge AXI_Bridge Root_Port_of_PCI_Express_Root_Complex X16 8.0_GT/s 512_bit true true true true 16 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=500 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[10].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[11].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[12].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[13].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[14].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[15].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[4].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[5].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[6].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[7].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[8].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[9].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=250 sys_clk=100 sys_clk_gt=100 47416 47806 18395 0 64 0 ADVANCE 1.14 09-15-2017
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x16g3_MS_32_ep_bridge AXI_Bridge PCI_Express_Endpoint_device X16 8.0_GT/s 512_bit true true true true 32 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=500 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[10].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[11].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[12].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[13].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[14].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[15].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[4].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[5].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[6].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[7].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[8].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[9].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=250 sys_clk=100 sys_clk_gt=100 47011 46367 17657 0 64 0 ADVANCE 1.14 09-15-2017
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x16g3_MS_32_rp_bridge AXI_Bridge Root_Port_of_PCI_Express_Root_Complex X16 8.0_GT/s 512_bit true true true true 32 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=500 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[10].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[11].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[12].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[13].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[14].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[15].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[4].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[5].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[6].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[7].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[8].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[9].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=250 sys_clk=100 sys_clk_gt=100 49356 48980 18785 0 64 0 ADVANCE 1.14 09-15-2017
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x16g3_MS_8_ep_bridge AXI_Bridge PCI_Express_Endpoint_device X16 8.0_GT/s 512_bit true true true true 8 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=500 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[10].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[11].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[12].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[13].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[14].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[15].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[4].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[5].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[6].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[7].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[8].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[9].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=250 sys_clk=100 sys_clk_gt=100 44474 44545 17006 0 64 0 ADVANCE 1.14 09-15-2017
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x16g3_MS_8_rp_bridge AXI_Bridge Root_Port_of_PCI_Express_Root_Complex X16 8.0_GT/s 512_bit true true true true 8 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=500 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[10].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[11].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[12].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[13].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[14].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[15].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[4].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[5].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[6].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[7].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[8].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[9].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=250 sys_clk=100 sys_clk_gt=100 46543 47136 18324 0 64 0 ADVANCE 1.14 09-15-2017
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x16g3_M_8_ep_bridge AXI_Bridge PCI_Express_Endpoint_device X16 8.0_GT/s 512_bit true true 8 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=500 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[10].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[11].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[12].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[13].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[14].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[15].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[4].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[5].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[6].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[7].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[8].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[9].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=250 sys_clk=100 sys_clk_gt=100 44474 44545 17006 0 64 0 ADVANCE 1.14 09-15-2017
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x16g3_M_8_rp_bridge AXI_Bridge Root_Port_of_PCI_Express_Root_Complex X16 8.0_GT/s 512_bit true true 8 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=500 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[10].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[11].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[12].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[13].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[14].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[15].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[4].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[5].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[6].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[7].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[8].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[9].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=250 sys_clk=100 sys_clk_gt=100 46543 47136 18324 0 64 0 ADVANCE 1.14 09-15-2017
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x16g3_S_8_ep_bridge AXI_Bridge PCI_Express_Endpoint_device X16 8.0_GT/s 512_bit true true 8 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=500 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[10].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[11].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[12].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[13].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[14].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[15].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[4].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[5].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[6].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[7].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[8].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[9].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=250 sys_clk=100 sys_clk_gt=100 44474 44545 17006 0 64 0 ADVANCE 1.14 09-15-2017
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x16g3_S_8_rp_bridge AXI_Bridge Root_Port_of_PCI_Express_Root_Complex X16 8.0_GT/s 512_bit true true DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=500 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[10].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[11].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[12].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[13].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[14].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[15].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[4].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[5].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[6].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[7].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[8].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[9].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=250 sys_clk=100 sys_clk_gt=100 46543 47136 18324 0 64 0 ADVANCE 1.14 09-15-2017
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x16g3_chnl1_mm X16 8.0_GT/s 512_bit 1 1 AXI_Memory_Mapped DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=500 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[10].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[11].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[12].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[13].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[14].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[15].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[4].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[5].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[6].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[7].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[8].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[9].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=250 sys_clk=100 sys_clk_gt=100 57854 53980 22788 0 78 0 ADVANCE 1.14 09-15-2017
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x16g3_chnl1_stream X16 8.0_GT/s 512_bit 1 1 AXI_Stream DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=500 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[10].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[11].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[12].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[13].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[14].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[15].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[4].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[5].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[6].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[7].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[8].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[9].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=250 sys_clk=100 sys_clk_gt=100 52805 52677 20487 0 79 0 ADVANCE 1.14 09-15-2017
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x16g3_chnl2_mm X16 8.0_GT/s 512_bit 2 2 AXI_Memory_Mapped DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=500 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[10].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[11].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[12].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[13].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[14].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[15].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[4].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[5].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[6].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[7].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[8].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[9].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=250 sys_clk=100 sys_clk_gt=100 63107 58974 24721 0 96 0 ADVANCE 1.14 09-15-2017
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x16g3_chnl2_stream X16 8.0_GT/s 512_bit 2 2 AXI_Stream DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=500 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[10].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[11].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[12].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[13].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[14].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[15].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[4].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[5].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[6].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[7].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[8].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[9].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=250 sys_clk=100 sys_clk_gt=100 63482 60452 23732 0 98 0 ADVANCE 1.14 09-15-2017
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x16g3_chnl4_mm X16 8.0_GT/s 512_bit 4 4 AXI_Memory_Mapped DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=500 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[10].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[11].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[12].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[13].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[14].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[15].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[4].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[5].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[6].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[7].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[8].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[9].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=250 sys_clk=100 sys_clk_gt=100 74711 69115 28847 0 132 0 ADVANCE 1.14 09-15-2017
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x16g3_chnl4_stream X16 8.0_GT/s 512_bit 4 4 AXI_Stream DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[24].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[25].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=500 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[10].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[11].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[12].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[13].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[14].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[15].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[4].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[5].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[6].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[7].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[8].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[9].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=250 sys_clk=100 sys_clk_gt=100 83084 75976 29761 0 136 0 ADVANCE 1.14 09-15-2017
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x1g1_chnl1_mm X1 2.5_GT/s 1 1 AXI_Memory_Mapped DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=250 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=125 sys_clk=100 sys_clk_gt=100 11836 14823 5865 0 33 0 ADVANCE 1.14 09-15-2017
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x1g1_chnl1_stream X1 2.5_GT/s 1 1 AXI_Stream DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=250 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=125 sys_clk=100 sys_clk_gt=100 10846 13491 5231 0 34 0 ADVANCE 1.14 09-15-2017
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x1g1_chnl4_mm X1 2.5_GT/s 4 4 AXI_Memory_Mapped DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=250 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=125 sys_clk=100 sys_clk_gt=100 26864 29819 12281 0 45 0 ADVANCE 1.14 09-15-2017
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x1g1_chnl4_stream X1 2.5_GT/s 4 4 AXI_Stream DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=250 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=125 sys_clk=100 sys_clk_gt=100 26593 27808 11618 0 49 0 ADVANCE 1.14 09-15-2017
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x1g1_ep_bridge AXI_Bridge PCI_Express_Endpoint_device X1 2.5_GT/s DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=250 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=125 sys_clk=100 sys_clk_gt=100 6995 9651 3181 0 29 0 ADVANCE 1.14 09-15-2017
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x1g1_rp_bridge AXI_Bridge Root_Port_of_PCI_Express_Root_Complex X1 2.5_GT/s DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=250 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=125 sys_clk=100 sys_clk_gt=100 8466 11478 3643 0 29 0 ADVANCE 1.14 09-15-2017
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x1g3_MS_8_ep_bridge AXI_Bridge PCI_Express_Endpoint_device X1 8.0_GT/s 64_bit true true true true 8 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=250 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=62 sys_clk=100 sys_clk_gt=100 7018 9765 3166 0 29 0 ADVANCE 1.14 09-15-2017
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x1g3_MS_8_rp_bridge AXI_Bridge Root_Port_of_PCI_Express_Root_Complex X1 8.0_GT/s 64_bit true true true true 8 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=250 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=62 sys_clk=100 sys_clk_gt=100 8493 11602 3629 0 29 0 ADVANCE 1.14 09-15-2017
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x1g3_M_8_ep_bridge AXI_Bridge PCI_Express_Endpoint_device X1 8.0_GT/s 64_bit true true 8 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=250 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=62 sys_clk=100 sys_clk_gt=100 7018 9765 3166 0 29 0 ADVANCE 1.14 09-15-2017
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x1g3_M_8_rp_bridge AXI_Bridge Root_Port_of_PCI_Express_Root_Complex X1 8.0_GT/s 64_bit true true 8 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=250 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=62 sys_clk=100 sys_clk_gt=100 8493 11602 3629 0 29 0 ADVANCE 1.14 09-15-2017
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x1g3_chnl1_mm X1 8.0_GT/s 64_bit 1 1 AXI_Memory_Mapped DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=250 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=62 sys_clk=100 sys_clk_gt=100 11851 14941 5852 0 33 0 ADVANCE 1.14 09-15-2017
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x1g3_chnl1_stream X1 8.0_GT/s 64_bit 1 1 AXI_Stream DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=250 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=62 sys_clk=100 sys_clk_gt=100 10898 13609 5272 0 34 0 ADVANCE 1.14 09-15-2017
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x1g3_chnl2_mm X1 8.0_GT/s 64_bit 2 2 AXI_Memory_Mapped DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=250 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=62 sys_clk=100 sys_clk_gt=100 16831 19909 8022 0 37 0 ADVANCE 1.14 09-15-2017
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x1g3_chnl2_stream X1 8.0_GT/s 64_bit 2 2 AXI_Stream DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=250 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=62 sys_clk=100 sys_clk_gt=100 15981 18379 7250 0 39 0 ADVANCE 1.14 09-15-2017
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x1g3_chnl4_mm X1 8.0_GT/s 64_bit 4 4 AXI_Memory_Mapped DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=250 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=62 sys_clk=100 sys_clk_gt=100 26828 29936 12237 0 45 0 ADVANCE 1.14 09-15-2017
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x1g3_chnl4_stream X1 8.0_GT/s 64_bit 4 4 AXI_Stream DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=250 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=62 sys_clk=100 sys_clk_gt=100 26587 27928 11564 0 49 0 ADVANCE 1.14 09-15-2017
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x1g3_ep_S_8_bridge AXI_Bridge PCI_Express_Endpoint_device X1 8.0_GT/s 64_bit true true DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=250 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=62 sys_clk=100 sys_clk_gt=100 7018 9765 3166 0 29 0 ADVANCE 1.14 09-15-2017
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x1g3_rp_S_8_bridge AXI_Bridge Root_Port_of_PCI_Express_Root_Complex X1 8.0_GT/s 64_bit true true DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=250 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=62 sys_clk=100 sys_clk_gt=100 8493 11602 3629 0 29 0 ADVANCE 1.14 09-15-2017
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x4g3_MS_8_ep_bridge AXI_Bridge PCI_Express_Endpoint_device X4 8.0_GT/s 128_bit true true true true 8 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=250 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=125 sys_clk=100 sys_clk_gt=100 10070 13462 4537 0 34 0 ADVANCE 1.14 09-15-2017
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x4g3_MS_8_rp_bridge AXI_Bridge Root_Port_of_PCI_Express_Root_Complex X4 8.0_GT/s 128_bit true true true true 8 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=250 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=125 sys_clk=100 sys_clk_gt=100 11403 15371 4941 0 34 0 ADVANCE 1.14 09-15-2017
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x4g3_M_8_ep_bridge AXI_Bridge PCI_Express_Endpoint_device X4 8.0_GT/s 128_bit true true 8 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=250 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=125 sys_clk=100 sys_clk_gt=100 10070 13462 4537 0 34 0 ADVANCE 1.14 09-15-2017
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x4g3_M_8_rp_bridge AXI_Bridge Root_Port_of_PCI_Express_Root_Complex X4 8.0_GT/s 128_bit true true 8 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=250 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=125 sys_clk=100 sys_clk_gt=100 11403 15371 4941 0 34 0 ADVANCE 1.14 09-15-2017
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x4g3_S_8_ep_bridge AXI_Bridge PCI_Express_Endpoint_device X4 8.0_GT/s 128_bit true true DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=250 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=125 sys_clk=100 sys_clk_gt=100 10070 13462 4537 0 34 0 ADVANCE 1.14 09-15-2017
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x4g3_S_8_rp_bridge AXI_Bridge Root_Port_of_PCI_Express_Root_Complex X4 8.0_GT/s 128_bit true true DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=250 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=125 sys_clk=100 sys_clk_gt=100 11403 15371 4941 0 34 0 ADVANCE 1.14 09-15-2017
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x4g3_chnl1_mm X4 8.0_GT/s 128_bit 1 1 AXI_Memory_Mapped DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=250 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=125 sys_clk=100 sys_clk_gt=100 15731 19180 7634 0 40 0 ADVANCE 1.14 09-15-2017
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x4g3_chnl1_stream X4 8.0_GT/s 128_bit 1 1 AXI_Stream DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=250 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=125 sys_clk=100 sys_clk_gt=100 14382 17847 6695 0 41 0 ADVANCE 1.14 09-15-2017
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x4g3_chnl2_mm X4 8.0_GT/s 128_bit 2 2 AXI_Memory_Mapped DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=250 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=125 sys_clk=100 sys_clk_gt=100 20824 24148 9910 0 46 0 ADVANCE 1.14 09-15-2017
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x4g3_chnl2_stream X4 8.0_GT/s 128_bit 2 2 AXI_Stream DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=250 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=125 sys_clk=100 sys_clk_gt=100 20080 23042 8997 0 48 0 ADVANCE 1.14 09-15-2017
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x4g3_chnl4_mm X4 8.0_GT/s 128_bit 4 4 AXI_Memory_Mapped DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=250 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=125 sys_clk=100 sys_clk_gt=100 30782 34201 14039 0 58 0 ADVANCE 1.14 09-15-2017
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x4g3_chnl4_stream X4 8.0_GT/s 128_bit 4 4 AXI_Stream DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=250 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=125 sys_clk=100 sys_clk_gt=100 31810 33472 13518 0 62 0 ADVANCE 1.14 09-15-2017
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x8g3_MS_8_ep_bridge AXI_Bridge PCI_Express_Endpoint_device X8 8.0_GT/s 256_bit true true true true 8 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=500 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[4].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[5].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[6].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[7].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=125 sys_clk=100 sys_clk_gt=100 16851 19550 7108 0 44 0 ADVANCE 1.14 09-15-2017
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x8g3_MS_8_rp_bridge AXI_Bridge Root_Port_of_PCI_Express_Root_Complex X8 8.0_GT/s 256_bit true true true true 8 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=500 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[4].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[5].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[6].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[7].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=125 sys_clk=100 sys_clk_gt=100 18424 21606 7765 0 44 0 ADVANCE 1.14 09-15-2017
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x8g3_M_8_ep_bridge AXI_Bridge PCI_Express_Endpoint_device X8 8.0_GT/s 256_bit true true 8 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=500 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[4].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[5].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[6].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[7].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=125 sys_clk=100 sys_clk_gt=100 16851 19550 7108 0 44 0 ADVANCE 1.14 09-15-2017
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x8g3_M_8_rp_bridge AXI_Bridge Root_Port_of_PCI_Express_Root_Complex X8 8.0_GT/s 256_bit true true 8 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=500 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[4].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[5].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[6].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[7].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=125 sys_clk=100 sys_clk_gt=100 18424 21606 7765 0 44 0 ADVANCE 1.14 09-15-2017
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x8g3_S_8_ep_bridge AXI_Bridge PCI_Express_Endpoint_device X8 8.0_GT/s 256_bit true true DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=500 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[4].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[5].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[6].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[7].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=125 sys_clk=100 sys_clk_gt=100 16851 19550 7108 0 44 0 ADVANCE 1.14 09-15-2017
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x8g3_S_8_rp_bridge AXI_Bridge Root_Port_of_PCI_Express_Root_Complex X8 8.0_GT/s 256_bit true true DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=500 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[4].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[5].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[6].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[7].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=125 sys_clk=100 sys_clk_gt=100 18424 21606 7765 0 44 0 ADVANCE 1.14 09-15-2017
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x8g3_chnl1_mm X8 8.0_GT/s 1 1 AXI_Memory_Mapped DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=500 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[4].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[5].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[6].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[7].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=125 sys_clk=100 sys_clk_gt=100 24687 26335 10478 0 52 0 ADVANCE 1.14 09-15-2017
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x8g3_chnl1_stream X8 8.0_GT/s 1 1 AXI_Stream DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=500 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[4].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[5].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[6].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[7].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=125 sys_clk=100 sys_clk_gt=100 22445 25001 9308 0 53 0 ADVANCE 1.14 09-15-2017
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x8g3_chnl2_mm X8 8.0_GT/s 256_bit 2 2 AXI_Memory_Mapped DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=500 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[4].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[5].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[6].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[7].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=125 sys_clk=100 sys_clk_gt=100 29807 31301 13068 0 62 0 ADVANCE 1.14 09-15-2017
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x8g3_chnl2_stream X8 8.0_GT/s 256_bit 2 2 AXI_Stream DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=500 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[4].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[5].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[6].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[7].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=125 sys_clk=100 sys_clk_gt=100 29342 31045 11884 0 64 0 ADVANCE 1.14 09-15-2017
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x8g3_chnl4_mm X8 8.0_GT/s 4 4 AXI_Memory_Mapped DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=500 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[4].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[5].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[6].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[7].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=125 sys_clk=100 sys_clk_gt=100 40278 41376 17210 0 82 0 ADVANCE 1.14 09-15-2017
xcvu3p ffvc1517 -3 xcvu3p-ffvc1517_x8g3_chnl4_stream X8 8.0_GT/s 4 4 AXI_Stream DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[26].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[1].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[2].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[27].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=500 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[1].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[2].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[4].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[5].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[6].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[7].gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=125 DUT/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O=1 axi_aclk=125 sys_clk=100 sys_clk_gt=100 43913 43191 17133 0 86 0 ADVANCE 1.14 09-15-2017

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