Sets supports_write to be 1, when supports_write is being set, ARM protocol Checker will check AW/W channel
Sets supports_write to be 0, when supports_write is not being set, ARM protocol Checker will not check AW/W channel
Sets supports_read to be 1, when supports_read is being set, ARM protocol Checker will check AR/R channel
Sets supports_read to be 0, when supports_read is not being set, ARM protocol Checker will not check AR/R channel
Sets xilinx_slave_ready_check_enable to turn on warning message when there is a violation of rules which arready/awready/wready should follow when the VIP goes into reset mode or comes out of reset mode. Which are 1).any READY must be low for the first clock edge that ARESETn goes high--PG101 XILINX_READY_RESET 2).READY must go low after 8 cycles following the first clock edge that ARESETn goes low--UG1037 Xilinx IP generally deasserts all VALID and READY outputs within eight cycles of reset.
Sets xilinx_slave_ready_check_enable to turn off warning message when there is a violation of rules which arready/awready/wready should follow when the VIP goes into reset mode or comes out of reset mode. Which are 1).any READY must be low for the first clock edge that ARESETn goes high--PG101 XILINX_READY_RESET 2).READY must go low after 8 cycles following the first clock edge that ARESETn goes low--UG1037 Xilinx IP generally deasserts all VALID and READY outputs within eight cycles of reset.
Sets xilinx_reset_check_enable to turn on error message when there is a violation of rule which is holding AXI ARESETN asserted for 16 cycles of the slowest AXI clock is generally a sufficient reset pulse width for Xilinx IP--UG1037
Sets xilinx_reset_check_enable to turn on warning message when there is a violation of rule which is holding AXI ARESETN asserted for 16 cycles of the slowest AXI clock is generally a sufficient reset pulse width for Xilinx IP--UG1037
Sets xilinx_reset_check_enable to turn off warning/error message when there is a violation of rule which is holding AXI ARESETN asserted for 16 cycles of the slowest AXI clock is generally a sufficient reset pulse width for Xilinx IP--UG1037
Sets xilinx_supports_narrow_burst_check_enable to turn on error message when a narrow burst is being detected while this VIP is in not support narrow burst mode.
Sets xilinx_supports_narrow_burst_check_enable to downgrade/upgrade to warning message when a narrow burst is being detected while this VIP is in not support narrow burst mode.
Sets xilinx_supports_narrow_burst_check_enable to downgrade error/warning into info message when a narrow burst is being detected while this VIP is in not support narrow burst mode.
Sets xilinx_no_strb_address_check_enable to turn on error message when address is being detected not aligned with data width while this VIP is in no strobe mode.
Sets xilinx_no_strb_address_check_enable to downgrade/upgrade to warning message when address is being detected not aligned with data width while this VIP is in no strobe mode.
Sets xilinx_no_strb_address_check_enable to downgrade error/warning into info message when address is being detected not aligned with data width while this VIP is in no strobe mode.
Sets xilinx_supports_narrow_cache_check_enable to turn on warning message when Cache[1] is not 1 while VIP is in no supports_narrow, has_cache mode.
Sets xilinx_supports_narrow_cache_check_enable to downgrade warning into info message when Cache[1] is not 1 while VIP is in no supports_narrow, has_cache mode.
Sets enable_xchecks to turn on error message when reset signal is unknown after 1 cycle of clock.
Sets enable_xchecks to downgrade/upgrade into warning message when reset signal is unknown after 1 cycle of clock.
Sets enable_xchecks to downgrade error/warning message into info message when reset signal is unknown after 1 cycle of clock.
Sets xilinx_write_response_check_enable to turn on error message when write response is not OKAY.
Sets xilinx_write_response_check_enable to downgrade/upgrade into warning message when write response is not OKAY.
Sets xilinx_write_response_check_enable to downgrade error/warning message into info message when write response is not OKAY.
Sets xilinx_read_response_check_enable to turn on error message when read response is not OKAY .
Sets xilinx_read_response_check_enable to downgrade/upgrade into warning message when read response is not OKAY.
Sets xilinx_read_response_check_enable to downgrade error/warning message into info message when read response is not OKAY.
Sets interface to slave mode
Sets interface to master mode
Sets interface to monitor mode
function longint unsigned calc_max_latency( |
| ); |
Determine if the current max latency is greater than the recently completed transaction.
function longint unsigned calc_running_avg( |
| ); |
Calculate the running average of the two values.
Return the current WRITE maximum latency value. Measured between the AW handshake to the B handshake.
Return the current READ maximum latency value. Measured between the AR handshake to the R handshake (with RLAST).
Return the current WRITE running average latency value. Measured between the AW handshake to the B handshake.
Return the current READ running average latency value. Measured between the AR handshake to the R handshake (with RLAST).