ISE
Design Entry Overview
Design entry is the first step in the ISE® design flow. During design entry, you create your source files based on your design objectives. You can create your top-level design file using a Hardware Description Language (HDL), such as VHDL, Verilog, or ABEL, or using a schematic. You specify your top-level module type when you create your project as described in Creating a Project.
You can use multiple formats for the lower-level source files in your design. Different source types are available, depending on your project properties (top-level module type, device type, synthesis tool, and language). You can create these source files in Project Navigator, as described in Creating a Source File. Some source types launch additional tools to help you create the file, as described in Source File Types.
Note If you converted your design to an EDIF or NGC/NGO file, you can skip the design entry processes and start with the implementation process.
Additional Resources
For information on creating efficient designs, such as setting up your design hierarchy and using good coding practices, refer to the following Xilinx® documentation:
DocumentationTopics Covered
Synthesis and Simulation Design GuideHigh-density design flow and recommended coding styles
XST User GuideHDL coding techniques
Development System Reference Guide Command line software programs in the Xilinx Development System
Application NotesTechnical details
See Also

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