FPGA Design Flow Overview

ISE

The ISE® design flow comprises the following steps: design entry, design synthesis, design implementation, and Xilinx® device programming. Design verification, which includes both functional verification and timing verification, takes places at different points during the design flow. This section describes what to do during each step. For additional details on each design step, click on a link below the following figure.

Design Entry

Create an ISE project as follows:

Create a project.
Create files and add them to your project, including a user constraints (UCF) file.
Add any existing files to your project.
Assign constraints such as timing constraints, pin assignments, and area constraints.

Functional Verification

You can verify the functionality of your design at different points in the design flow as follows:

Before synthesis, run behavioral simulation (also known as RTL simulation).
After Translate, run functional simulation (also known as gate-level simulation), using the SIMPRIM library.
After device programming, run in-circuit verification.

Design Synthesis

Synthesize your design.

Design Implementation

Implement your design as follows:

Implement your design, which includes the following steps:
- Translate
- Map
- Place and Route
Review reports generated by the Implement Design process, such as the Map Report or Place & Route Report, and change any of the following to improve your design:
- Process properties
- Constraints
- Source files
Synthesize and implement your design again until design requirements are met.

Timing Verification

You can verify the timing of your design at different points in the design flow as follows:

Run static timing analysis at the following points in the design flow:
- After Map
- After Place & Route
Run timing simulation at the following points in the design flow:
- After Map (for a partial timing analysis of CLB and IOB delays)
- After Place and Route (for full timing analysis of block and net delays)

Xilinx Device Programming

Program your Xilinx device as follows:

Create a programming file (BIT) to program your FPGA.
Generate a PROM or ACE file for debugging or to download to your device. Optionally, create a JTAG file.
Use iMPACT to program the device with a programming cable.