You can use a hardware description language (HDL), such as VHDL,
Verilog, or ABEL (for CPLDs), for your top-level or lower-level design
files. HDL files describe the behavior and structure of system and
circuit designs. Using HDLs to design high-density devices allows
you to do the following:
- Use a top-down approach
You can use HDLs to create complex
designs that require many designers to work together. After an overall
plan is determined, each designer works on a separate section of the
- Run functional simulation early in the design cycle
can verify your design functionality early in the flow by simulating
the HDL description. Testing your design decisions at the register
transfer level (RTL) or gate level before the design is implemented
allows you to make changes early in the design process.
- Use a synthesis engine to translate your design to gates
Synthesis decreases design time by eliminating the need to define
every gate. Synthesis to gates reduces the number of errors that may
occur during a manual translation of the hardware description to a
schematic design. Also, the synthesis tool can apply automation, such
as machine encoding styles or automatic I/O insertion during optimization,
resulting in greater efficiency.
- Retarget your code to different architectures
use the same HDL design for new architectures with a minimum of recoding.
This works especially well if you inferred, rather than instantiated,
components. For details, see Instantiation and
on the advantages of using HDLs are available in the following Xilinx® documentation:
Review this documentation and consult any of the many
HDL textbooks available. In addition, you can enroll in any of the Xilinx® training
classes available from the Xilinx website
. Click Training
to view the available classes and to sign up.