ISE
Working with Language Templates
The ISE® Language Templates provide prepared pieces of code and code syntax for use in your source files. These templates enable easy insertion of pre-built text structures into your VHDL, Verilog, ABEL, Tcl, or UCF source file. There are several types of pre-built templates available, such as common language structures or instantiation templates for synthesis.
Note For information on instantiation and inference, see Instantiation and Inference.
To Open a Language Template
To open the Language Templates provided by Xilinx®, do the following:
  1.  Select Edit > Language Templates.
  2.  In the Language Templates window that opens in the Project Navigator Workspace, click the plus (+) icon next to one of the following folders: ABEL, Tcl, COREGEN, UCF, Verilog, VHDL.
    Note The COREGEN folder is only available if you are using CORE Generator™ IP in an FPGA design.
  3.  Click the plus (+) icon to expand the folders until you find the template you want to use.
  4.  Select the template to display it in the right pane.
    Note You cannot edit the Language Templates provided by Xilinx.
To Use a Language Template
You can add the code from the template to your HDL file using any of the following methods.
Note After adding the code, you must edit the inserted code to make it specific to your design. Text that requires editing is denoted by angle brackets (<>), for example, <clock> must be changed to the clock name referenced in the design.
Use in File Method
  1.  In your source file, place your cursor where you want the template to be inserted.
  2.  In the Language Templates window, select a Language Template.
  3.  Select Edit > Use in file. The code from the template appears in your file.
Copy and Paste Method
  1.  In the Language Templates window, open a template.
  2.  Right-click in the template, and select Select All.
  3.  Select Edit > Copy.
  4.  In your source file, place your cursor where you want the template to be inserted.
  5.  Select Edit > Paste to paste the template into your file.
Drag and Drop Method
  1.  In the Language Templates window, open a template.
  2.  Right-click in the template, and select Select All.
  3.  Drag the highlighted text to the desired location in your source file.
  4.  Release the mouse button to drop the template into your file.
To Create a Language Template
You can create your own custom language templates for easy access to frequently used code as follows:
  1.  In the Language Templates window in the Project Navigator Workspace, click the plus (+) icon next to one of the following folders: ABEL, Tcl, Verilog, or VHDL.
  2.  Select the User Templates folder.
  3.  To create a folder to contain your template, select Edit > New Folder.
  4.  Type a name for your folder.
  5.  Select Edit > New Template.
  6.  Type a name for your template.
  7.  Add your code to the right pane of the Language Template window.
  8.  To save your template to your project, select File > Save.
Note To remove a template, click the name of your template and select Edit > Delete.

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