CORE Generator
Implementing an HDL Design Containing Cores
To implement a design containing cores, the core implementation netlists must be merged into the main design. This is done automatically when the NGDBuild program is run on the top level netlist.
The NGDBuild program is described in the "NGDBuild" chapter of the Command Line Tools User Guide.
When you merge the core netlists into the main design using NGDBuild:
  •  Verify that all of the CORE Generator™ EDN netlists and NGC netlists for the generated modules are located in the project directory.
  •  Place all the EDIF and NGC files associated with the design in a separate directory and run NGDBuild with the -sd option to specify explicitly the location of the directory containing the CORE Generator implementation netlist files.
If you are implementing your design within ISE® software, you can set the Macro Search Path in the Process Properties dialog box for the Translate process to specify the location of this directory.
The output of NGDBuild is an NGD file, which contains a logical description of your design in terms of both its original components and hierarchy and the Xilinx® NGD primitives to which the design is reduced. This file is the input to the mapping, place and route, and bitstream generation programs through which your design is implemented in the Xilinx device.
See Also

© Copyright 1995–2009, Xilinx® Inc. All rights reserved.