CORE Generator
Synthesizing a Verilog Design Containing Cores
To synthesize the parent design containing your cores, follow the vendor specific instructions in the table below for integrating a black box module into your design. If needed, please refer to your synthesis vendor documentation for more details.
Most synthesis tools automatically infer a black box upon encountering a Verilog module declaration, which only contains port directional declarations. The logic for each core is specified in either an EDIF or NGC implementation netlist (component_name.edn or  component_name.ngc) and, for some cores, may also be specified in additional NGC files, but it is not specified in the Verilog wrapper file for the core.
Note   For Synplicity only, direct the synthesizer to treat each core as a black box if necessary.
Synthesis Vendor ToolSpecial Instructions
Mentor Graphics Synthesis PrecisionDo not read in a separate V or NGC file for the CORE Generator™ module. Mentor Graphics automatically treats the module as a black box.
Synopsys FPGA Compiler IINo special instructions.
Synplicity SynplifyAnalyze the V wrapper file in Synplify. The CORE Generator attaches the appropriate black_box attribute to the core’s module declaration in the V wrapper file for the module. Analyzing the V wrapper file is sufficient to prevent black box warnings from Synplify during compilation.
ISE® (Xilinx XST)No special instructions.
The following example shows how the CORE Generator configures the module declaration for the core as a Verilog black box for Synplicity:
module myadder8(
A,
B,
C_IN,
Q,
CLK);     // synthesis black_box
input [7 : 0] A;
input [7 : 0] B;
input C_IN;
output [7 : 0] Q;
input CLK;
// synopsys translate_off
//  (List of core customization parameters omitted)
inst (
  .A(A),
  .B(B),
  .C_IN(C_IN),
  .Q(Q),
  .CLK(CLK),
//  (Other optional 3rd party black box attributes
//  omitted)
// synopsys translate_on
endmodule
After the parent design has been synthesized, the synthesis tool writes out its NGC implementation netlist.
You have the option of either breaking buses out into their individual bus bits, or maintaining them as a single array (B<n:m>, B(n:m), or B<[n:m]) when writing out the implementation netlist for a module. The bus format chosen should be consistent with the bus format chosen when you set Project Options. The bus format is set in the Generation Panel of the Project Options dialog box.
These vendor tools write out an NGC netlist for a Xilinx® design:
  •  Mentor Graphics Precision Synthesis
  •  Synopsys FPGA Compiler II
  •  Synplicity Synplify
See Also

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