CORE Generator
Synthesizing a VHDL Design Containing Cores
To synthesize the parent design containing your cores, follow the vendor specific instructions in the table below for integrating a black box module into your design. If needed, please refer to your synthesis vendor documentation for more details.
In most cases you must not add the VHD wrapper for the core to your synthesis project or analyze it as part of your synthesis flow. Additionally, although the CORE Generator™ VHO template files continue to specify black box attributes for the supported synthesis vendors, attachment of black box attributes is now optional for most vendors.
The logic for each core is specified in an NGC implementation netlist  component_name.ngc) and, for some cores, may also be specified in additional NGC files, but it is not specified in the VHD wrapper file for the core.
Synthesis Vendor ToolSpecial Instructions
Mentor Graphics Precision SynthesisDo not read in a separate VHD or NGC file for the CORE Generator module. Mentor Graphics automatically treats the module as a black box.
Synopsys FPGA Compiler IINo special instructions.
Synplicity SynplifyDo not read in a separate VHD or NGC file for the CORE Generator module. It is also recommended that you attach a syn_black_box attribute to the component declaration for the CORE Generator module as indicated in the VHO template generated for the core. This attribute is optional but prevents Synplicity from issuing warnings about black box modules.
ISE® (Xilinx XST)No special instructions.
A sample VHDL black box COMPONENT definition is shown below:
component myadder8
port (
A: IN std_logic_VECTOR(7 downto 0);
B: IN std_logic_VECTOR(7 downto 0);
C_IN: IN std_logic;
Q: OUT std_logic_VECTOR(7 downto 0);
CLK: IN std_logic);
end component;
-- Synplicity black box declaration
attribute syn_black_box : boolean;
attribute syn_black_box of myadder8: component is true;
After the parent design has been synthesized, the synthesis tool writes out its EDIF or NGC implementation netlist.
You have the option of either breaking buses out into their individual bus bits, or maintaining them as a single array (B<n:m>, B(n:m), or B<[n:m]) when writing out the implementation netlist for a module. The bus format chosen should be consistent with the bus format chosen when you set Project Options. The bus format is set in the Generation panel of the Project Options dialog box.
These vendor tools write out an EDIF netlist for a Xilinx® design:
  •  Mentor Graphics Precision Synthesis
  •  Synopsys FPGA Compiler II
  •  Synplicity Synplify
See Also

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