CORE Generator
Performing Behavioral Simulation on a Verilog Design Containing Cores
When you analyze the simulation netlist, be sure to include the V wrapper file for the core. The table below describes compile and simulation commands for all Xilinx® supported simulation vendors. In the table, adder_tb.v is the test bench, myadder8_top.v is the parent design file, and myadder8.v is the wrapper file for the myadder8 core.
Simulation VendorSetup File SettingsCommands
MTINone
vlib work
vmap XilinxCoreLib <compiled_XilinxCoreLib>
vlog adder_tb.v myadder8_top.v myadder8.v
vsim -Lf Xilinx CoreLib adder_tb
NC-Verilog
In cds.lib, add:
DEFINE XilinxCoreLib {compiled_XilinxCoreLib}
ncvlog adder_tb.v myadder8_top.v myadder8.v
ncelab -message adder_tb
ncsim -run adder_tb
VCS/VCSiNone
vcs -Mupdate
-Mlib=<compiled_XilinxCoreLib>
-y $XILINX/verilog/src/XilinxCoreLib
+libext+.v +incdir+ $XILINX/verilog/src
-R  adder_tb.v myadder8_top.v myadder8.v
Verilog-XLNone
verilog +incdir+$XILINX/verilog/src
-y <src_XilinxCoreLib>
+libext+.v
adder_tb.v myadder8_top.v
myadder8.v
See Also
Verilog Design Flow (Standalone)

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