CORE Generator
Creating a Test Bench for a Verilog Design Containing Cores
To simulate a design containing a core, create a test bench file. The test bench should instantiate the top level module and should contain stimuli to drive the input ports of the design. The following example displays the framework for a test bench file used to simulate a design, with some sample simulation stimuli. The test bench file is named adder_tb.v.
Verilog Test Bench File:  adder_tb.v
’timescale 1 ns/1 ps
module adder_tb;
reg CLKT;
reg C_INT;
reg [7:0] AT;
reg [7:0] BT;
wire [8:0] QT;
/* Instantiation of top level design */
myadder8_top uut (
/* Add stimulus here */
always #10 CLKT = ~CLKT;
initial begin
initial begin
C_INT = 0;
AT = 0;
BT = 0;
CLKT = 1;
AT = 8’b10000000;
BT = 8’b00000001;
AT = 8’b11100001;
BT = 8’b00000010;
#1000 $stop;
// #1000 $finish;
/* end stimulus section */
See Also

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