Instantiating Cores in a Verilog Design
When you select Verilog as your design flow, the following files
are generated to instantiate each core you create in the CORE Generator™ system:
- A Verilog instantiation template file, component_name.veo, which contains a module template for the core.
- An implementation netlist component_name.ngc.
- A wrapper file, component_name.v, for functional simulation of the core.
The core template file (component_name.veo) for each generated core must be instantiated into
the parent design.
To Instantiate a Core in a Verilog Design
- Copy the module template from the core’s instantiation template
(VEO file) into the appropriate areas of the Verilog module.
- In the Verilog module, change YourInstanceName (a dummy name from the instantiation template) to the actual instance
- In the Verilog module, modify the port connections copied from
the instantiation template to reflect the actual connections to the
The instantiation template (VEO file) contains instructions
describing how the core is instantiated into the parent design. For
more details, see Core
Instantiation Example - Verilog
The component declaration
and component instantiation block establish a link in the Verilog
code to the implementation netlist for the CORE Generator module. This
link is necessary to ensure that the core is integrated properly when
the parent Verilog design has been synthesized. The Verilog instantiation
of the core in the parent design serves as a placeholder for the core.
During design implementation the Xilinx® tools merge the core’s NGC netlists with the rest of the parent design.
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