CORE Generator
Core Instantiation Example - Verilog
This example illustrates the use of a VEO instantiation template file in a parent design. In the example, an 8-bit registered adder named myadder8 generated by the CORE Generator™ system, is instantiated in a parent design.
The files of interest are:
  •  The parent design: myadder8_top.v
  •  The instantiation template file produced by the CORE Generator system: myadder8.veo
  •  The wrapper file, which is produced by the CORE Generator system and is used for functional simulation of the core:  myadder.v
Verilog Template File:  myadder8.veo
The Verilog template file shown below was produced when the CORE Generator generated the myadder8 core.
*                                                                        *
*     Xilinx products are not intended for use in life support           *
*     appliances, devices, or systems. Use in such applications are      *
*     expressly prohibited.                                              *
*                                                                        *
*     (c) Copyright 1995-2007 Xilinx, Inc.                               *
*     All rights reserved.                                               *
*************************************************************************/
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
myadder8 YourInstanceName (
.A(A),
.B(B),
.C_IN(C_IN),
.Q(Q),
.CLK(CLK));
// INST_TAG_END ------ End INSTANTIATION Template ---------
// You must compile the wrapper file myadder8.v when simulating
// the core, myadder8. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
The wrapper file myadder8.v, referred to in the file above, is generated by the CORE Generator along with the implementation netlist and VEO file when Verilog outputs are requested. The wrapper file binds the customized core to the corresponding XilinxCoreLib Verilog behavioral simulation model, and also passes the Verilog model parameters which customize the model. The wrapper file must be analyzed during behavioral simulation.
Verilog Parent Design File:  myadder8_top.v
The parent design, myadder8_top.v, is shown below. The template code (with dummy signal names replaced with actual signal names) has been cut and pasted into the parent file from myadder8.veo. Also, the dummy instance name (YourInstanceName) has been replaced with the actual instance name.
//------------------------------------------------
module myadder8_top (A_P, B_P, C_INP, Q_P, CLK_P);
input [7 : 0] A_P;
input [7 : 0] B_P;
input C_INP;
output [8 : 0] Q_P;
input CLK_P;
// INST_TAG
myadder8 uut(
.A(A_P),
.B(B_P),
.C_IN(C_INP),
.Q(Q_P),
.CLK(CLK_P));
// INST_TAG_END
endmodule
See Also

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