Performing Behavioral Simulation with ModelSim on a VHDL Design Containing Cores

CORE Generator

Before the ModelSim simulation tools can be used to simulate the design, the wrapper file for the module, the parent design, and the test bench need to be analyzed. These design files are analyzed with the vcom command into a local, default, work library, created using the vlib command.

To Perform Behavioral Simulation on a VHDL Design

Start up ModelSim in the project_directory.
To analyze the wrapper file, the parent design, and the test bench file, type the following:
```
vlib work
vcom design_name.vhd
vcom design_name_top.vhd 
vcom design_name_tb.vhd
```
Invoke the simulator by typing in the following command:
```
vsim design_name_tb
```