CORE Generator
VHDL Design Flow (Standalone)
The following design flow describes the procedure for behavioral simulation, synthesis, and implementation of VHDL designs containing CORE Generator™ modules using the following vendor tools:
Xilinx® XST
FPGA Compiler II
Mentor Graphics
Precision Synthesis
Synplicity Synplify
SimulationMTI ModelSim/VLOG
VHDL Design Flow
  1.  If you are performing functional simulation on your design with a 3rd-party simulator, compile the XilinxCoreLib library. Image
  2.  Start the CORE Generator. Image
  3.  Create a new CORE Generator project. Image
    When the Project Options dialog box appears as part of creating the new project, select the following in the Generation panel of the dialog box:
    •  In the Flow section, select Design Entry and VHDL.
    •  In the Flow Settings section, select the appropriate Vendor. The Vendor setting specifies the synthesis vendor tool you use for your design and fills in the proper Netlist Bus Format in the dialog box. The proper Netlist Bus Format permits you to integrate the implementation netlist into the upper level parent VHDL file.
  4.  In the CORE Generator window, create the customized cores you want to use in your design. Image
  5.  Instantiate the cores you have created. Image
  6.  Create a test bench. Image
  7.  Perform behavioral simulation. Image
  8.  Synthesize the design. Image
  9.  Implement the design. Image

© Copyright 1995–2009, Xilinx® Inc. All rights reserved.