CORE Generator
Instantiating Cores in a VHDL Design
When you select VHDL as your preferred language, the following files will be generated for instantiating each core you create in the CORE Generator™ system:
  •  A VHDL implementation template file, component_name.vho, which contains these items:
    •  Component declaration
    •  Component instantiation
  •  An implementation netlist, component_name.edn or component_name.ngc.
  •   For some cores, one or more lower level NGC netlists.
  •  A wrapper file, component_name.vhd, for functional simulation of the core.
The core template file (component_name.vho) for each generated core must be instantiated into the parent design.
To Instantiate a Core in a VHDL Design
  1.  Copy the component declaration and the instantiation from the core’s instantiation template (VHO file) into the appropriate areas of the parent design.
  2.  In the parent design, change your_instance_name (a dummy name from the instantiation template) to the actual instance name.
  3.  In the parent design, modify the port connections copied from the instantiation template to reflect the actual connections to the parent design.
The instantiation template (VHO file) contains instructions describing how the core is instantiated into the parent design. For more details, see Core Instantiation Example - VHDL.
The component declaration and component instantiation block establish a link in the VHDL code to the NGC netlist for the CORE Generator module. This link is necessary to ensure that the core is integrated properly when the parent VHDL design has been synthesized. The VHDL instantiation of the core in the parent design serves as a placeholder for the core. During design implementation the Xilinx® tools merge the core’s NGC netlists with the rest of the parent design.
See Also

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