CORE Generator
Core Instantiation Example - VHDL
This example illustrates the use of a VHO instantiation template file in a parent design. In the example, an 8-bit registered adder named myadder8 generated by the CORE Generator™ system, is instantiated in a parent design.
The files of interest are:
  •  The parent design: myadder8_top.vhd
  •  The instantiation template file produced by the CORE Generator system: myadder8.vho
  •  The wrapper file, which is produced by the CORE Generator system and is used for functional simulation of the core:  myadder.vhd
VHDL Template File:  myadder8.vho
The VHDL template file shown below was produced when the CORE Generator generated the myadder8 core.
-------------------------------------------------------------------------
--    This file is owned and controlled by Xilinx and must be used     --
--    solely for design, simulation, implementation and creation of    --
--    design files limited to Xilinx devices or technologies. Use      --
--    with non-Xilinx devices or technologies is expressly prohibited  --
--    and immediately terminates your license.                         --
--                                                                     --
--    Xilinx IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"    --
--    SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR          --
--    Xilinx DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION  --
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-------------------------------------------------------------------------
-- The following code must appear in the VHDL architecture header:
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
component myadder8
port (
A: IN std_logic_VECTOR(7 downto 0);
B: IN std_logic_VECTOR(7 downto 0);
C_IN: IN std_logic;
Q: OUT std_logic_VECTOR(7 downto 0);
CLK: IN std_logic;
end component;
-- FPGA Express Black Box declaration
attribute fpga_dont_touch: string;
attribute fpga_dont_touch of myadder8: component is "true";
-- Synplicity black box declaration
attribute syn_black_box : boolean;
attribute syn_black_box of myadder8: component is true;
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
-- The following code must appear in the VHDL architecture
-- body. Substitute your own instance name and net names.
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
your_instance_name : myadder8
port map (
  A => A,
  B => B,
  C_IN => C_IN),
  Q => Q,
  CLK => CLK);
-- INST_TAG_END ------ End INSTANTIATION Template ------------
-- You must compile the wrapper file myadder8.vhd when simulating
-- the core, myadder8. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
The wrapper file myadder8.vhd, referred to in the file above, is generated by the CORE Generator systemalong with the EDIF (or NGC) netlist and VHO file when VHDL outputs are requested. The wrapper file contains a Configuration Specification which binds the customized core to the corresponding XilinxCoreLib VHDL behavioral simulation model, and also passes the VHDL model generics which customize the model. The wrapper file must be analyzed during behavioral simulation.
VHDL Parent Design File:  myadder8_top.vhd
The parent design, myadder8_top.vhd, is shown below. The component declaration and the instantiation (with dummy signal names replaced with actual signal names) have been cut and pasted into the parent file from myadder8.vho.
library IEEE;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_1164.all;
ENTITY myadder8_top IS
PORT (
AP:  IN std_logic_vector(7 downto 0);
BP: IN std_logic_vector(7 downto 0);
C_INP: IN std_logic ;
QP: OUT std_logic_VECTOR (8 downto 0);
CLKP: IN  std_logic);
END myadder8_top;
ARCHITECTURE use_core of myadder8_top IS
--------------------------------------------------------
---- The MYADDER8 core is used in this design. The
---- core must be declared via a ’component declaration’; 
---- myadder8.vho provides the component declaration 
---- which is cut and pasted into the design as 
---- shown below. 
------------------------------------------------------- 
component myadder8
port (
A: IN std_logic_VECTOR(7 downto 0);
B: IN std_logic_VECTOR(7 downto 0);
C_IN: IN std_logic;
Q: OUT std_logic_VECTOR(8 downto 0);
CLK: IN std_logic
);
end component;
-- FPGA Express Black Box declaration
attribute fpga_dont_touch: string;
attribute fpga_dont_touch of myadder8: component is "true";
-- Synplicity black box declaration
attribute syn_black_box : boolean;
attribute syn_black_box of myadder8: component is true;
BEGIN
--------------------------------------------------------
---- The core is instantiated into this design. 
---- myadder8.vho provides an instantiation 
---- template which must be modified
---- so that it reflects actual signals used in the 
---- design, establishing the connectivity between the 
---- core and other logic at this level.  The instance 
---- of the core must also be given an actual label to 
---- replace the dummy "your_instance_name" tag. In this 
---- example,it is replaced by "myadder8_1". 
--------------------------------------------------------
myadder8_1 : myadder8
port map (
A => AP,
B => BP,
C_IN => C_INP,
Q => QP,
CLK => CLKP
);
end use_core;
See Also

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