CORE Generator
Generation Panel - Project Options Dialog Box
Use this dialog box to specify the files that are produced when a core is generated in the current project.
  •  Flow
    •  Design Entry
      Enables you to specify your Electronic Design Automation (EDA) flow (Schematic, VHDL or Verilog) and design entry vendor. You can specify any of the following design entry flows.
      •  VHDL
        The CORE Generator™ produces a VHO instantiation template file and a VHD file. The VHO template file contains commented VHDL example code that can be used to instantiate a CORE Generator module in a VHDL design. The VHD file is used to support functional simulation of the core. See the Simulation Files option described below.
      •  Verilog
        The CORE Generator produces a VEO instantiation template file and V wrapper file. The VEO template file contains commented Verilog example code that can be used to instantiate a CORE Generator module in a Verilog design. The V wrapper file is used to support functional simulation of the core.
      •  Schematic
        Depending on your chosen Vendor, the CORE Generator customizes the output files appropriately. The correct Netlist Bus Format is selected and additional output products are generated if necessary.
        •  Cadence
          The CORE Generator produces a netlist withCadence compatible Bus Format.
        •  ISE
          The CORE Generator produces an ASCII symbol (ASY) file, a Schematic Editor symbol (SYM) file (for the Xilinx® Schematic Editor), and the underlying netlist.
        •  Other
          The CORE Generator produces a netlist with the Netlist Bus Format you specify.
    •  Custom Output Products
      Enables you to select explicitly the Output Products the CORE Generator produces for each generated module.
  •  Flow Settings
    •  Vendor
      Specifies your design entry vendor.
      If you select any vendor except Other, the CORE Generator automatically sets the Netlist Bus Format to the correct value for that vendor. If you set the Design Entry vendor to Other, you also need to specify the Netlist Bus Format.
    •  Netlist Bus Format
      Sets the format in which bus signals are written in the output Netlist file. If you select Other as your design entry vendor, you have to set a Netlist Bus Format.
      Bus format can be specified as a single array. For these options, B represents the name of the bus and n:m represent the range of the bus index. Options are B<n:m>, B[n:m], and B(n:m)
      Note Support for the generation of IP implementation netlists containing bus port names split into individual bus bits ("bit-blasted" format) is still available as a project option for the 9.1i CORE Generator release, but this support is deprecated and is not available in the next release of ISE® software. ISE 9.1i is the last release to support this bus format as a project option. Note that there are a number of cores which do not support individual bus bit format for the Implementation Netlist at all. These include the Binary Counter, FIFO Generator, and all Ethernet cores.
  •  Simulation Files
    Specifies the file type the CORE Generator generates for simulating your design.
    •  Behavioral
      For each core generated, produces an HDL file that can be used to simulate the core. The file is one of the following:
      •  A wrapper file that instantiates a XilinxCoreLib model.
      •  A simulation model based on a mixture of structural components and XilinxCoreLib models.
      The contents of the file depend on what is available for the core being generated.
    •  Structural
      Produces a structural simulation netlist for each core generated.
      Note   The structural simulation netlist should not be used for synthesis.
    •  None
      The CORE Generator does not generate any simulation files.
  •  Prefered Language
    Specifies the language of your simulation environment.
    •  VHDL
      Generates files for simulating a generated core in a VHDL simulation environment.
    •  Verilog
      Generates files for simulating a generated core in a Verilog simulation environment.
  •  Other Output Products
    •  ASY Symbol File
      If selected, the CORE Generator generates an ASY symbol file. This is an ASCII symbol information file used by the ISE tools and some third party interface tools to create a symbol representing the core.
See Also

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