Generation Panel - Project Options Dialog Box
Use this dialog box to specify the files that are produced
when a core is generated in the current project.
- Flow Settings
Specifies your design entry vendor.
If you select any vendor except Other,
the CORE Generator automatically sets the Netlist Bus Format to the correct
value for that vendor. If you set the Design Entry vendor to Other, you also need to specify the Netlist
- Netlist Bus Format
Sets the format in which bus signals are written in the output
Netlist file. If you select Other as your design
entry vendor, you have to set a Netlist Bus Format.
Bus format can be specified as a single array. For
these options, B represents the name of the bus and n:m represent
the range of the bus index. Options are B<n:m>
, and B(n:m)
Note Support for the generation of IP implementation
netlists containing bus port names split into individual bus bits
("bit-blasted" format) is still available as a project option for
the 9.1i CORE Generator release, but this support is deprecated and is
not available in the next release of ISE® software. ISE 9.1i
is the last release to support this bus format as a project option.
Note that there are a number of cores which do not support individual
bus bit format for the Implementation Netlist at all. These include
the Binary Counter, FIFO Generator, and all Ethernet cores.
- Simulation Files
Specifies the file type the CORE Generator generates for simulating
- Prefered Language
Specifies the language of your simulation environment.
- Other Output Products
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