CORE Generator
CORE Generator Output Files
ASY File
A graphical symbol information file used by the ISE® tools and some third party interface tools to create a symbol representing the core.
File List (flist.txt) File
The File List file, which is named generated_core_name_flist.txt, is a text file listing all of the output files produced when a customized core was generated in the CORE Generator™ system.
MIF File
Memory Initialization File which is automatically generated by the CORE Generator system for some CORE Generator modules when an HDL simulation flow is specified. A MIF data file is used to support HDL functional simulation of modules which use arrays of values. Examples include memories, FIR filters, and bit correlators.
NCF File
Xilinx NCF (Netlist Constraints File). The file is an NCF template containing constraints generated when a core is elaborated.
NDF File
An optional output file produced for cores that generate NGC files. The NDF files allow third party synthesis tools to infer resource utilization and timing from the NGC files associated with these cores.
NGC File
A binary Xilinx implementation netlist. The logic implementation of certain CORE Generator IP is described by a combination of a top level EDN or NGC and possibly one or more lower level NGC files.
padded.ngc File
The padded.ngc file, which is named generated_core_name_padded.edn, is an NGC wrapper file generated for a core when the Generate netlist wrapper with IO pads project option is enabled. The file adds input pads and output pads to the core, enabling you to process the generated core through the Xilinx design flow as if it were a complete chip design.
Readme File
The Readme file, which is named generated_core_name_readme.txt, lists the output files produced when a core is generated and describes each file.
SYM File
Schematic symbol file used to instantiate a generated core into the ISE Schematic Editor.
UCF File
Xilinx UCF (User Constraints File). The file is a UCF template containing constraints generated when a core is elaborated. The constraints in the file are cut and pasted into the UCF file of an ISE project.
All Architecture Wizard cores, and some other IP cores, generate UCF files. 
V File
Verilog wrapper file, which is used to support Verilog functional simulation of a core. The V wrapper passes customized parameters to the generic core simulation model. For more information, see Verilog Design Flow (Standalone).
If the V output file is named core_name_for.v, the file supports formal verification.
VEO File
Verilog template file. The components in this file can be used to instantiate a core. For more information, see Verilog Design Flow (Standalone).
VHD File
VHDL wrapper file, which is used to support VHDL functional simulation of a core. The VHD wrapper passes customized parameters to the generic core simulation model. For more information, see VHDL Design Flow (Standalone).
VHO File
VHDL template file. The components in this file can be used to instantiate a core. For more information, see VHDL Design Flow (Standalone).
XAW File
As an output file, the XAW file is a binary file that holds the configuration settings for an Architecture Wizard core. The CORE Generator system generates an XAW file in the project directory for each Architecture Wizard core that it creates.
An XAW file can also be used as an input to the CORE Generator.
XCO File
As an output file, the XCO file stores the project and core parameter settings used to generate a particular core. The CORE Generator generates an XCO file in the project directory for each IP core that it creates.
An XCO file can also be used as an input to the CORE Generator.
XSF File
A Xilinx Netlist Format port list file used by the Mentor Graphics tools to create a symbol representing the core.

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