Design Entry Overview

ISE

Design entry is the first step in the ISE® design flow. During design entry, you create source files to represent your design. The top-level design source file can be any of the following formats:

Hardware Description Language (HDL), such as VHDL or Verilog
Schematic (SCH)
Embedded processor (XMP)
EDIF or NGC/NGO file (if you choose to synthesize your design outside of Project Navigator)

For HDL and schematic top-level designs, lower-level source files can be multiple formats, including HDL, schematic, IP, and netlist. For EDIF or NGC/NGO netlist top-level designs, the EDIF or NGC/NGO file is the only source file allowed in the project.

You can create new source files that are automatically added to your project as described in Creating a Source File. You can also add existing source files to your project as described in Adding a Source File to a Project. For more information on source files, see Source File Types. Some source file types may not be available, depending on your design properties (top-level module type, target device, and synthesis tool).

Note You cannot add lower-level EDIF or NGC/NGO netlists directly to a project. However, if the design contains lower-level netlists, these files are automatically linked to the design during the Translate step of the Implement Design process. The lower-level netlists must be in the same directory as the top-level netlist, or you must point to the lower-level netlists using the Macro Search Path property in the Translate Properties dialog box.

Additional Resources

Additional information is available in the following Xilinx® documentation.

Documentation	Topics Covered
Synthesis and Simulation Design Guide	High-density design flow and recommended coding styles
XST User Guide	HDL coding techniques
Command Line Tools User Guide	Command line software programs in the Xilinx Development System
Application Notes	Technical details