You can use a Hardware Description Language (HDL), such as VHDL or Verilog, for your top-level
or lower-level design files. HDL files describe the behavior and structure
of system and circuit designs. Using HDLs allows you to do the following:
- Use a synthesis engine to translate your design to gates
Synthesis decreases design time by eliminating the need to define
every gate. In addition, the synthesis tool can apply automation,
such as machine encoding styles or automatic I/O insertion during
optimization, resulting in greater efficiency.
- Run functional simulation early in the design cycle
can verify your design functionality early in the flow by simulating
the HDL description. Testing your design at the Register Transfer Level (RTL) or gate level
before the design is implemented allows you to make changes early
in the design process.
- Retarget your code to different architectures
use the same HDL design for new architectures with a minimum of recoding.
This works especially well if you inferred, rather than instantiated,
Additional information is available
in the following Xilinx® documentation.
In addition, you can consult any of the many HDL
textbooks available. You can also enroll in Xilinx training classes,
available from the Training
page of the Xilinx website.