Using schematics for your top-level
or lower-level design files allows you to have a visual representation
of your design. You can use schematics for your top-level design,
your lower-level design files, or both, as follows:
- Top-level schematic
You can use a schematic as your top-level
design and create the lower-level modules using any of the following
source types: HDL files, CORE Generator™ cores, Architecture Wizard IP, or schematic
files. To instantiate a lower-level module in your top-level design,
you must create a schematic symbol from the lower-level module, and
instantiate the schematic symbol. For information on schematic symbols,
see Creating a Schematic Symbol
. For more information on top-level
schematics, see Creating a Top-Level Schematic
Note You do not need to create schematic symbols for CORE Generator cores
or for Xilinx® Unified Library symbols. The CORE Generator software automatically
generates schematic symbols, and library symbols are predefined. The CORE Generator software
and Architecture Wizard are not supported for CPLDs.
- Lower-level schematic
You can use schematics to define
the lower-level modules of your design. If the top-level design file
is a schematic, you must create a schematic symbol from the lower-level
schematic, and then instantiate the symbol in the top-level schematic.
If the top-level design file is an HDL file, you must create an HDL
instantiation template from the schematic, and then instantiate the
template in the top-level HDL file. For more information, see Creating a Lower-Level
All schematics are ultimately converted to either VHDL or Verilog
structural netlists before being passed on to your synthesis tool
during the Synthesize process.
Note You cannot run the Schematic and Symbol Editors directly
from the command line. This software must be launched from Project Navigator.
Additional information is available in
the following Xilinx documentation.