ISE
Simulation Libraries
Most designs are built with generic code, so device-specific components are not necessary. However, in certain cases, it may be required or beneficial to use device-specific components in the code to achieve the desired end circuit implementation and results. When you instantiate a component in your design, the simulator must reference a library that describes the functionality of the component to ensure proper simulation. Xilinx® provides the following simulation libraries for simulating primitives and cores:
  •  UNISIM library for functional simulation of Xilinx primitives
  •  UniMacro library for functional simulation of Xilinx macros
  •  XilinxCoreLib library for functional simulation of Xilinx cores
  •  Xilinx EDK library for behavioral simulation of Xilinx Embedded Development Kit (EDK) IP components
  •  SIMPRIM library for timing simulation of Xilinx primitives
  •  SmartModel/SecureIP simulation library for both functional and timing simulation of Xilinx Hard-IP, such as PPC, PCIe®, GT, and TEMAC IP.
Note For additional information on simulation libraries, see the Synthesis and Simulation Design Guide. For details on device primitives, see the Libraries Guides.
UNISIM Library
The UNISIM library is used during functional simulation and contains descriptions for all the device primitives, or lowest-level building blocks. You must specify the UNISIM library anytime you include a device primitive listed in the Libraries Guides in your source code. Specify this library as follows:
  •  VHDL
    Add the following library declaration to the top of your HDL file:
    library UNISIM;  
    use UNISIM.Vcomponents.all;
    Using this declaration, the simulator references the functional models for all device primitives. When using third party simulators, you must also compile the library and map the library to the simulator in addition to this declaration. This is covered in the "Simulation Library Compilation" section below.
  •  Verilog
    When you invoke the simulator from within Project Navigator, the simulator script automatically references the UNISIMS_VER library. When using third party simulators, you must also compile the library and map the library to the simulator. This is covered in the "Simulation Library Compilation" section below.
    If you are running the simulator outside of Project Navigator, the UNISIMS_VER library must be referenced to the simulator. The method used to reference this library depends on the simulator. Please refer to the documentation for your simulator.
UniMacro Library
The UniMacro library is used during functional simulation and contains macro descriptions for selective device primitives. You must specify the UniMacro library anytime you include a device macro listed in the Libraries Guides in your source code. Specify this library as follows:
  •  VHDL
    Add the following library declaration to the top of your HDL file:
    library UNIMACRO;  
    use UNIMACRO.Vcomponents.all;
    Using this declaration, the simulator references the macros for all device primitives. When using third party simulators, you must also compile the library and map the library to the simulator in addition to this declaration. This is covered in the "Simulation Library Compilation" section below.
  •  Verilog
    When you invoke the simulator from within Project Navigator, the simulator script automatically references the UniMacro_VER library. When using third party simulators, you must also compile the library and map the library to the simulator. This is covered in the "Simulation Library Compilation" section below.
    If you are running the simulator outside of Project Navigator, the UniMacro_VER library must be referenced to the simulator. The method used to reference this library depends on the simulator. Please refer to the documentation for your simulator.
Note This library does not apply to CPLDs.
XilinxCoreLib Library
the XilinxCoreLib library is used during functional simulation for designs that contain certain cores created by the Xilinx CORE Generator™ software. This library is specified as follows:
  •  VHDL
    The CORE Generator software automatically generates a VHD file, which is a VHDL wrapper file that includes the library declaration. When using third party simulators, you must also compile the library and map the library to the simulator. This is covered in the "Simulation Library Compilation" section below.
  •  Verilog
    When you invoke the simulator from within Project Navigator, the simulator script automatically references the XilinxCoreLib_VER library, and the CORE Generator software generates a V file, which is a Verilog wrapper file. When using third party simulators, you must also compile the library and map the library to the simulator. This is covered in the "Simulation Library Compilation" section below.
    If you are running the simulator outside of Project Navigator, the XilinxCoreLib_VER library must be referenced to the simulator. The method used to reference this library depends on the simulator. Please refer to the documentation for your simulator.
Note This library does not apply to CPLDs. For information on cores, see the CORE Generator Help. In the Help Viewer, click the Synchronize TOC button Image to view all related Help topics.
Xilinx EDK Library
The EDK library is used for behavioral simulation and contains all EDK IP components that are precompiled for ModelSim SE and PE or NCSim. This library eliminates the need to recompile EDK components on a per-project basis, which minimizes overall compile time. The EDK IP components library is provided for VHDL only and may be encrypted. The Xilinx Compxlib utility deploys compiled models for EDK IP components into a common location. Unencrypted EDK IP components can be compiled using Compxlib. Precompiled libraries are provided for encrypted components.
Note For information on EDK, see the Embedded Development Kit Documentation. For information on Compxlib options and capabilities, see the Command Line Tools User Guide, or type the following at the command line: compxlib -help.
SIMPRIM Library
The SIMPRIM library is used for structural simulation netlists produced after implementation, including timing simulation. This library is specified as follows:
  •  VHDL
    The library declaration is automatically written by the netlist. When using third party simulators, you must also compile the library and map the library to the simulator. This is covered in the "Simulation Library Compilation" section below.
  •  Verilog
    When you invoke the simulator from within Project Navigator, the simulator script automatically references the SIMPRIMS_VER library.  When using third party simulators, you must also compile the library and map the library to the simulator. This is covered in the "Simulation Library Compilation" section below.
    If you are running the simulator outside of the Project Navigator environment, the SIMPRIMS_VER library must be referenced to the simulator. The method used to reference this library depends on the simulator. Please refer to the documentation for your simulator.
SmartModel/SecureIP Simulation Library
The SmartModel/SecureIP library is used for the functional and timing simulation of complex FPGA components, such as the PPC and the GT components. To simulate these complex Hard-IP components, see the Synthesis and Simulation Design Guide.
Note This library does not apply to CPLDs.
Simulation Library Compilation
Before you can simulate your design, you must compile the applicable libraries and map them to the simulator. The Project Navigator Compile HDL Simulation Libraries process automates this task. It compiles all of the relevant libraries for a given device family and writes a library mapping file to the project directory in which it was invoked. For details on running this process, see Compiling HDL Simulation Libraries.
If you want to compile the libraries outside of Project Navigator, you can run the Compxlib program from the command line. For information on Compxlib options and capabilities, see the Command Line Tools User Guide, or type the following at the command line: compxlib -help.
Note You do not need to compile or map Xilinx Simulation Libraries if you are using the ISim or the ModelSim Xilinx Edition simulator.
See Also

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