Running the Generate Programming File Process for FPGAs
run the Generate Programming File process after your FPGA design is
completely placed and routed (PAR). The Generate Programming File
process runs BitGen, the Xilinx® bitstream generation
program, to produce a bitstream (BIT or ISC file) for Xilinx device
configuration. This includes the software application data from the
ELF file as follows:
- If you added an ELF file directly to the ISE project, this
ELF file is automatically included in the bitstream generated by the
Generate Programming File process.
- If the software component of the embedded processor system
is generated in XPS as part of the XMP project and the ELF file
was not added directly to the ISE project,
you can run the Update Bitstream with Processor Data process to bring the
software application data contained in the system ELF file into the
The programming file is saved in your project directory.
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