Running the Generate Programming File Process for FPGAs
You can run the Generate Programming File process after your FPGA design is completely placed and routed (PAR). The Generate Programming File process runs BitGen, the Xilinx® bitstream generation program, to produce a bitstream (BIT or ISC file) for Xilinx device configuration. This includes the software application data from the ELF file as follows:
  •  If you added an ELF file directly to the ISE project, this ELF file is automatically included in the bitstream generated by the Generate Programming File process.
  •  If the software component of the embedded processor system is generated in XPS as part of the XMP project and the ELF file was not added directly to the ISE project, you can run the Update Bitstream with Processor Data process to bring the software application data contained in the system ELF file into the bitstream.
Note For information on Xilinx device configuration, see the Configuration and Programming Overview.
To Run the Generate Programming File Process
  1.  In the Design panel, select Implementation from the Design View drop-down list. Image
  2.  In the Hierarchy pane, select the top module Image.
  3.  Optional. In the Processes pane, right-click the Generate Programming File process, and select Process Properties to set properties for the process in the following dialog boxes. Image
  4.  In the Processes pane, double-click Generate Programming File.
The programming file is saved in your project directory.
After running this process, you can perform any of the following:
  •  Check the report generated by the Generate Programming File process. Image
  •  Generate a PROM or ACE file. Image
  •  Generate a Boundary Scan (JTAG) file. Image
  •  Configure or program a target device. Image

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