ISE
Schematic to HDL Netlist Conventions
The VHDL and Verilog netlisters use the following conventions when generating the HDL functional model for a schematic.
Schematic to VHDL Netlist Conventions
The VHDL netlister uses the following conventions:
  •  The name of the schematic becomes the name of the top-level entity.
  •  Each net name flagged with an I/O marker is declared as a port in the declaration.
  •  The architecture name is always the schematic name.
  •  Scalar nets become VHDL signals of type >std_logic.
  •  Buses become VHDL signals of type >std_logic_vector.
  •  Component declarations are generated in the architecture for each type of symbol instantiated in the schematic.
  •  A component instantiation is created for each symbol instance in the schematic. The symbol instance name becomes the instantiation label.
  •  Each symbol pin becomes a port on the corresponding component.
Schematic to Verilog Netlist Conventions
The Verilog netlister uses the following conventions:
  •  The name of the schematic becomes the name of the top-level module.
  •  Each net name flagged with an I/O marker is declared as a port in the declaration.
  •  Scalar nets become Verilog wires.
  •  Buses become Verilog wires of equivalent widths.
  •  Module declarations are generated for each type of symbol instantiated in the schematic.
  •  A module instantiation is created for each symbol instance in the schematic. The symbol instance name becomes the instantiation label.
  •  Each symbol pin becomes a port on the corresponding module.
See Also

© Copyright 1995–2009, Xilinx® Inc. All rights reserved.