Compiling HDL Simulation Libraries
need to compile the simulation libraries to the compiled library directory
before using them for design simulations. Xilinx® provides an application
called Compxlib that enables you to compile the HDL libraries for
all Xilinx-supported simulators. This utility compiles the VHDL and
Verilog UNISIM, SIMPRIM, XilinxCoreLib, and Xilinx EDK libraries
for all supported device architectures.
To Compile HDL Simulation Libraries
- In the Hierarchy pane of the Design panel, select
the device entry (for example, xcv50-6bg256).
- In the Processes pane, expand Design Utilities.
- Right-click the Compile HDL Simulation Libraries process, and select Process Properties.
- In the Simulation
Library Compiler Properties dialog box, select the target simulator
and the libraries you want to compile.
Note The Target Simulator property value must be specified before starting compilation.
- In the Processes pane, double-click Compile
HDL Simulation Libraries.
The simulation libraries will be compiled and put in a
directory specified in the Compiled Library Directory property in
the Simulation Library Compiler Properties dialog box.
After running this process, you can perform any of the
- View the compilation log.
- Simulate your design.
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