Compiling HDL Simulation Libraries
You need to compile the simulation libraries to the compiled library directory before using them for design simulations. Xilinx® provides an application called Compxlib that enables you to compile the HDL libraries for all Xilinx-supported simulators. This utility compiles the VHDL and Verilog UNISIM, SIMPRIM, XilinxCoreLib, and Xilinx EDK libraries for all supported device architectures.
Note For more information about the libraries and Compxlib commands, see Simulation Libraries.
To Compile HDL Simulation Libraries
  1.  In the Hierarchy pane of the Design panel, select the device entry (for example, Image xcv50-6bg256).
  2.  In the Processes pane, expand Design Utilities.
  3.  Right-click the Compile HDL Simulation Libraries process, and select Process Properties.
  4.  In the Simulation Library Compiler Properties dialog box, select the target simulator and the libraries you want to compile.
    Note The Target Simulator property value must be specified before starting compilation.
  5.  In the Processes pane, double-click Compile HDL Simulation Libraries.
The simulation libraries will be compiled and put in a directory specified in the Compiled Library Directory property in the Simulation Library Compiler Properties dialog box.
After running this process, you can perform any of the following:
  •  View the compilation log. Image
  •  Simulate your design.

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