I/O Pin Planning — Pre-Synthesis
You can assign input and output (I/O) signals to package pins in your design. This process launches the PlanAhead™ software for FPGA designs and Pinout and Area Constraints Editor (PACE) for CPLD designs. Using the editor, you can assign I/O locations, specify I/O banks, specify I/O standards, prohibit I/O locations, and create legal pin assignments using the built-in design rule checks (DRC). This process operates on the top module in your design before the design is synthesized. This allows you to assign input and output signals to package pins before the underlying logic in the design has been developed.
Constraints are saved to a user constraints file User Constraints File (UCF). You can create the UCF file prior to running this process, as described in Creating a Source File, or you can allow the software to create an empty UCF file.
To Assign I/O Pins — Pre-Synthesis
  1.  In the Design panel, select Implementation from the Design View drop-down list. Image
  2.  In the Hierarchy pane, select the top module Image or the associated UCF file.
  3.  In the Processes pane, expand User Constraints, and do one of the following:
    •  For FPGAs, double-click I/O Pin Planning (PlanAhead) - Pre-Synthesis.
    •  For CPLDs, double-click Floorplan IO - Pre-Synthesis.
For FPGA designs, the PlanAhead software opens with the PinAhead environment loaded. The PlanAhead software extracts the top-level I/O port information from the associated HDL source files. If a UCF file is associated with your ISE® project, it is passed to the PlanAhead software for modification. If a UCF file does not exist, an empty one is created for you. If multiple UCF files exist, you are prompted to select the file to which you want to add new constraints. Existing constraints are modified in their respective files. For more information, see the “I/O Pin Planning” chapter of the PlanAhead User Guide.
Note After updating constraints in the PlanAhead software, you must save the PlanAhead project and exit the PlanAhead software. This updates the UCF files in the ISE project and updates the ISE project status accordingly. If you do not save and exit from the PlanAhead software, the ISE project and UCF files are not updated.
For CPLD designs, the UCF associated with the top module is displayed in PACE and you can assign I/O package pins for your design in the UCF. For more information, see the PACE Help.
After running this process, you can run the synthesize process. Image

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