This file describes the new features in the Xilinx® ISE® Design Suite 11 software release. It contains the following sections.
Note: You can disable this page from opening when ISE Design Suite starts. From the Project Navigator workspace, Select Edit > Preferences > ISE General and deselect Open What's New document at startup.
What's New in ISE Design Suite 11.4
The following sections describe changes in ISE Design Suite for 11.4.
Introducing Spartan-6 and Virtex-6 Device Support
Xilinx introduces the following Spartan®-6 and Virtex®-6 device support for the 11.4 release:
New Device Support
Spartan-6:
Support for -4 speedgrade
LX4 Device support
Support for Spartan-6 Lower Power (-1L) devices
Support for Spartan-6 XA Automotive devices
Virtex-6
Support for -3 speedgrade for HXT devices
What's New in Logic Design Tools
The following describes what’s new in ChipScope™, FPGA Editor, PlanAhead™, XPower, and XST.
ChipScope Enhancements
Parameter sweep feature in IBERT 2.0 for Spartan-6 LXT.
Channel test that sweep through various transceiver settings and allows measurement of transceiver performance characteristics across that range of settings.
Core generation of IBERT 2.0 (Integrated Bit Error Ratio Test) cores for Virtex-6 HXT.
ChipScope Analyzer will support interaction with GTX transceivers in the Virtex-6 HXT devices.
FPGA Editor Enhancements
Improvements providing smaller memory footprint and faster design load time.
PlanAhead Enhancements
New Simultaneous Switching Noise (SSN) prediction tool for Virtex-6 I/0 Planning.
XPower Estimator Enhancements
Junction Temperature calculation up to 125C.
XST Enhancements
New MUX_MIN_SIZE constraint. Improves the device utilization for designs targeting Virtex-6 and Spartan-6 families.
What's New in Simulation Libraries
Compxlib support for Modelsim DE product offering.
What's New in Embedded Tools and IP
EDK Enhancements
Base System Builder support for the Spartan-6 SP601 board.
Flashwriter and GenACE support for the SP601.
Base System Builder support for the Virtex-6 ML605 board.
Flashwriter and GenACE support for the ML605.
MicroBlaze updated to V7.20.d.
Virtex-6 System Monitor support.
What's New in DSP Tools and IP
System Generator Enhancements
Introducing support for the following device families:
Spartan-6 XA
Spartan-6 -1L
Ease of use and tool flow integration
Support added for MATLAB 2009b
Support the Ethernet hardware co-simulation on the Virtex-6 ML605 platform
IP Integration
Updated Building Blocks
Complex Multiplier 3.1
DSP48 Macro 2.0
Updated Forward Error Correction (FEC) blocks
Reed Solomon Encoder 7.0
Reed Solomon Decoder 7.0
Convolution Encoder 7.0
Viterbi Decoder 7.0
Interleaver/de-interleaver 5.1
AccelDSP Synthesis Tool
This is the final release of the AccelDSP synthesis tool. Further development of the AccelDSP synthesis tool has been discontinued. You can continue to use this version of the tool with ISE Design Suite 11. The tool will not be included in ISE Design Suite 12.
What's New in CORE Generator and IP
New IP Cores
Connectivity IP
10 Gigabit Ethernet PCS/PMA (10GBASE-R): Full-rate serial interface for 10 Gigabit Ethernet MAC.
DisplayPort: New serial protocol for high bandwidth Broadcast, Medical, and Consumer Display applications supporting transmission rates up to 2.75 Gbps.
Virtex-6 GTH Transceiver Wizard: New OTU-1, OTU-4, OC-48 and OC-192 protocol templates.
Spartan-6 GTP Transceiver Wizard - New XAUI protocol template.
DSP IP
DSP48 Macro: An easy to use graphical user interface which abstracts the XtremeDSP Slice configuration and simplifies its dynamic operation via a set of user defined mathematical expressions.
Video IP
Image Edge Enhancement: A fast and easy to use hardware block for enhancing the edges within a video image frame.
Image Noise Reduction: An easy to use image processing block for reducing noise within single or multiple image frames.
Image Statistics Engine: Performs hardware image analysis to support automatic focus, exposures, and white balance.
Motion Adaptive Noise Reduction: A high quality and easily configurable motion adaptive noise reduction function or integration within a wide variety of imaging applications.
Wireless IP
3GPP LTE MIMO Decoder: Resource optimized and scalable MIMO decode function for 3GPP-LTE basestations.
3GPP LTE RACH Detector: A flexible and highly optimized RACH detection function required for 3GPP-LTE basestations
Peak Cancellation Crest Factor Reduction (PC-CFR): Highly optimized and flexible CFR solution for cellular basestations.
What's New in ISE Design Suite 11.3
The following sections describe changes in ISE Design Suite for 11.3.
Introducing Virtex-6 HXT FPGA Device Support
Xilinx introduces the Virtex®-6 HXT family of FPGAs targeted at ultra high bandwith serial system solutions. This family is supported by the following tools:
General Design, Power, and Implementation Tools
Complete support for Virtex-6 HXT devices
Bitgen supports DRC only for Virtex-6 HXT devices in 11.3
System Generator
Support for Virtex-6 HXT devices, as well as for Virtex-6 Lower Power and Virtex-5Q devices.
What's New in Logic Design Tools
The following describes what’s new in ISE Foundation™, ISE WebPACK™ software, ISim, PlanAhead™, ChipScope™ Pro, and ChipScope Pro Serial I/O Toolkit.
Project Navigator Enhancements
Updated Start panel provides quick access to recent projects and additional resources.
New Layout menu commands allow you to save, load, and share different layouts for the panels and toolbars in the main window.
New Compare Projects feature available from the Project Browser allows you to compare the settings and source file contents for two selected projects.
Usability improvements in the Design Panel:
New radio buttons in the Design Panel to easily switch to the simulation views to run simulation when using ISim or ModelSim simulators.
Files Tab now lists the View Association and Library information for all source files in the project.
ChipScope Pro Enhancements
Added Integrated Bit Error Ratio Tester (IBERT) 2.0 for Spartan®-6 LXT FPGA devices.
iMPACT Enhancements
eFUSE reading and programming is supported for Spartan-6 devices.
eFUSE support has been extended to Linux in addition to Windows (32-bit versions only).
ISE HDL Templates
Instantiation templates have been organized according to the devices they support. This enhances the capability to identify the correct component for a specific architecture.
ISim Enhancements
The following usability enhancements have been made to ISim. For more information, refer to the ISim User Guide.
Added the ability to change the default Radix and Radix for Object Window. You can now view signals in the objects window using the Radix of your choice.
Improvements to Marker/Measurement in the waveform editor. Steps to measure values are significantly simpler.
The Design Unit name now displays in the Instance window. You can sort by the Design Unit name in addition to instantiation names.
PlanAhead Enhancements
Support for creation of DCI Cascade groups and membership editing
GUI Enhancement to label pin rows in package view when zoomed in
Additional Design Rule Checks (DRCs) for Virtex-6 and Spartan-6 devices
Power Analyzer (XPA)
Added ability to interrupt a Power Analysis process.
Added bus reconstruction in I/O view.
Added ability to select and edit multiple cells.
EDK Enhancements
Windows XP and Windows Vista installations now use Cygwin version 1.5.25.
Platform Flash XL now supported (command line only).
Contract-based IP licensing is now supported.
SDK suspend/terminate issue is now resolved.
Clock Generator support for Virtex-6 and Spartan-6 in XPS.
Clock wizard support for MPMC in Virtex-6 and Spartan-6.
Pre-production support for Virtex-6 CXT family.
What's New in DSP Tools and IP
System Generator Enhancements
Support for the following devices:
Virtex-6 HXT
Virtex-6 Lower Power (Virtex-6 -1L)
Virtex-5Q
Support for JTAG hardware co-simulation for the Spartan-6 SP605 Evaluation Kit.
Support for the following operating systems:
Windows Vista Business 32-bit (English)
Red Hat Enterprise Desktop 5.2 (32 and 64-bit)
SUSE Linux Enterprise 10 (32 and 64-bit)
Discontinuation of support for FSL (Fast Simplex Link): Starting with Release 11.3, further development of System Generator support for the FSL bus on the EDK Processor block has been discontinued. You can continue to use FSL with ISE Design Suite 11, but support for the FSL will not be included in ISE Design Suite 12.
Xilinx Blockset Enhancements
DDS Compiler 4.0
This block is now available in System Generator with the following features:
New option added to use the block as a Phase Generator or SIN/COS Lookup Table only. This capability allows you to customize the Direct Digital Synthesizer to fit your individual application needs.
Increased Spurious Free Dynamic Range (SFDR) from 120 dB to 150 dB.
Option to configure DDS using system-level parameters (SFDR, Frequency resolution) or hardware parameters (Phase and output width).
Option to trade off XtremeDSP™ slice usage for maximum performance.
Option to configure phase increment and phase offset as constant, programmable, or dynamic (for modulation).
Note: This block supersedes the DDS Compiler 3.0 block. DDS Compiler version 4.0 is not bit-accurate with respect to earlier versions. Also, latency of phase offset effects has been balanced with the latency of phase increments for ease of use in the streaming modes. This change also applies to existing programmable and fixed modes.
CIC Compiler 1.3
This block is now available in System Generator with the following features:
Supports Virtex-6 and Spartan-6.
Input and output streaming interface added for multiple channel implementations.
Capability added to specify hardware over sampling specification as a sample period.
Capability added to leverage over sampling factor to optimize resource utilization.
Note: This block supersedes the CIC Compiler 1.2 block. The RATE_WE signal no longer acts as a reset to the core; the core will update to the new rate on the next input sample (for a single channel implementation) or the next input to the first channel (for multiple channel implementations).
Additional IP
The following blocks were upgraded to support the latest version of the LogiCORE (with no change in block functionality):
Multiplier LogiCORE v11.2: Leverages speed and area optimization for LUT implementation.
Block Memory Generator v3.3: Upgraded to add Virtex-6 Lower Power (Virtex-6 -1L), Virtex-6 HXT, and Virtex-5Q support.
Distributed Memory Generator v4.2: Upgraded to add Virtex-6 Lower Power (Virtex-6 -1L), Virtex-6 HXT, and Virtex-5Q support.
FIFO Generator v5.3: Upgraded to add Virtex-6 Lower Power (Virtex-6 -1L), Virtex-6 HXT, and Virtex-5Q support.
Upsample Block
A new Latency parameter has been added.AccelDSP Synthesis Tool
Further development of the AccelDSP synthesis tool has been discontinued. You can continue to use this version of the tool with ISE Design Suite 11. The tool will not be included in ISE Design Suite 12.
What's New in CORE Generator and IP
New IP Cores
FPGA Features and Design
Spartan-6 SelectIO Wizard v1.1: generates an HDL file that contains IO logic such as IOSERDES and IODELAY blocks customized to the user's interface requirements.
Virtex-6 FPGA GTH Transceiver Wizard v1.1: generates a custom wrapper that configures one or more Virtex-6 FPGA GTH transceivers according to user requirements. In addition, it produces an example design, testbench, and scripts that allow you to observe the transceivers operating under simulation and in hardware.
Video and Image Processing
Video On Screen Display v1.0: a sophisticated module that provides three hardware accelerated functions including multiple alpha blending layer compository, simplified graphics processing unit (boxes), and simplified text processing unit for video systems.
Video Direct Memory Access v1.0: a sophisticated module that allows Video Cores to access external memory via the Video Frame Buffer Controller (VFBC) within the MultiPort Memory Controller (MPMC) under control of the host processor.
Communication and Networking
RXAUI v1.1: The Xilinx Reduced Pin 10 Gigabit Attachment Unit Interface (RXAUI) LogiCORE IP provides a 2-lane high speed serial interface, providing up to 10 Gigabits per second (Gbps) total throughput. Operating at an internal clock speed of 156.25 MHz, the core includes the Dune Networks RXAUI implementation, the XGMII Extender Sublayers (DTE and PHY XGXS), and the 10GBASE-X sublayer, as described in clauses 47 and 48 of IEEE 802.3-2005. The core supports an optional serial MDIO management interface for accessing the IEEE 802.3-2005 clause 45 management registers.
IP Core Updates
Support for Virtex-6 HXT, Virtex-6 Lower Power, and Virtex-5Q have been added to selected cores in this release.
A comprehensive listing of cores that have been updated in the 11.3 release can be viewed at www.xilinx.com/ipcenter/coregen/11_3_datasheets.htm.
For more information, refer to www.xilinx.com/ipcenter/coregen/updates_11_3.htm.
New CORE Generator Features
CORE Generator checks for IP license availability before proceeding through the core generation process.
Automated core upgrade to latest version capability has been added for the following IP cores:
CIC Compiler v1.3
DDS Compiler v4.0
Distributed Memory Generator v4.2
Multiplier Generator v11.2
What's New in ISE Design Suite 11.2
The following sections describe changes in the ISE Design Suite for 11.2.
Introducing Virtex-6 and Spartan-6 Device Support
Experience a complete software flow for the new Virtex-6 and Spartan-6 targeted design platforms. Many applications have new features specifically added to enhance Virtex-6 and Spartan-6 performance, as described below:
New VHDL/Verilog Parser for XST for Virtex-6 and Spartan-6
Support for complex data structures
Fixes long standing complexity problems, such as long runtime and memory usage
Greater flexibility in design coding
Easier migration of designs to Xilinx architectures
Faster runtime for Virtex-6 and Spartan-6 compared to preceding families
Timing Analyzer
Multi-Corner Timing Analysis leveraged for improved timing analysis for Virtex-6
Timing Analysis support for Virtex-6 and Spartan-6 ICAP component
Asynchronous path tracing enabled for Virtex-6 and Spartan-6
Setup/hold (recovery/removal) checking on asynchronous pin of registers enabled by default
Configuration simulation model enhancements
Support for ICAP for Spartan-6 and Virtex-6
Serial configuration supported in SIM_CONFIG models
SelectMAP configuration support for Virtex-6 and Spartan-6
Power Optimization and Analysis
Easier comparison between device families in XPE
Combined XPE spreadsheets for Spartan-3A and Spartan-6
Combined XPE spreadsheets for Virtex-5 and Virtex-6
iMPACT
eFUSE reading and programming is supported for Virtex-6 devices
PlanAhead
Support for I/O assignment for Virtex-6 and Spartan-6 devices
Support for Design Rule Checks for Virtex-6 and Spartan-6 devices
Support for floorplanning and LOC constraints for designs targeting Virtex-6 and Spartan-6 parts
ChipScope
Integrated Bit Error Ratio Tester (IBERT) 2.0 for Virtex-6
Graphical visualization of parameter sweep results
Similar look and feel as Rocket IO Wizard
Improved system clocking, including higher frequencies and ability to use REFCLK as system clock
Xilinx Platform Studio (XPS)
Pre-production support for Spartan-6 and Virtex-6 FPGA Families
Embedded IP
Pre-production support for Spartan-6 and Virtex-6 families
LUT-6 optimization for MicroBlaze™ processors in Spartan-6 and Virtex-6 families
System Generator and AccelDSP Enhancements
Support for Virtex-6 and Spartan-6
Support for Virtex-6 Hardware Co-Simulation (ML605 Platform)
New Blocks Now Available in System Generator
DDS Compiler 3.0: Supports Virtex-6 and Spartan-6
Divider Generator 3.0: Supports Virtex-6 and Spartan-6
Fast Fourier Transform 7.0: Supports Virtex-6 and Spartan-6
FIR Compiler 5.0: Supports Virtex-6 and Spartan-6
New IP Cores
Bus Interface and IO
Spartan-6 Integrated Block for PCI Express v1.1 - The Xilinx Spartan-6 Integrated Block for PCI Express uses the Spartan-6 Integrated Hard IP Block for PCI Express in conjunction with flexible Spartan-6 architectural features to implement a compliant PCI Express Endpoint.
Virtex-6 Integrated Block for PCI Express v1.2 - The Xilinx Virtex-6 Integrated Block for PCI Express (1-lane, 2-lane, 4-lane, and 8-lane) uses the Virtex-6 Integrated Hard IP Block for PCI Express in conjunction with flexible Virtex-6 architectural features to implement a PCI Express Base Specification v2.0 compliant PCI Express Endpoint. Unique features of the LogiCORE Block for PCI Express are the high performance LocalLink User Interface, optimal buffering for high bandwidth applications, and BAR checking and filtering.
Communication and networking
Virtex-6 Embedded Tri-Mode Ethernet MAC Wrapper v1.2 – automates generation of HDL wrapper files with the correct attributes and physical interfaces for the user-selected configuration of the Virtex-6 Embedded Tri-Mode Ethernet MAC.
FPGA features and design
Spartan-6 FPGA RocketIO GTP Transceiver Wizard - automates generation of HDL wrapper files with the correct attributes and physical interfaces for Spartan-6 FPGA GTPA1 transceivers.
Virtex-6 FPGA RocketIO GTX Transceiver Wizard - automates generation of HDL wrapper files with the correct attributes and physical interfaces for Virtex-6 FPGA GTX transceivers.
IP Core Updates for Virtex-6 and Spartan-6
A comprehensive listing of cores that have been updated with support for Virtex-6 and Spartan-6 in this release can be viewed at www.xilinx.com/ipcenter/coregen/11_2_datasheets.htm.
For more information see www.xilinx.com/ipcenter/coregen/updates.htm.
What's New in Logic Design Tools
The following describes what’s new in ISE Foundation, ISE WebPACK™ software, ISim, PlanAhead, ChipScope Pro, and ChipScope Pro Serial I/O Toolkit:
Multi-Threading Support Added for Place and Route on Windows
Usability Improvements
Project Navigator
Improvements to Project Navigator "Find-in-Files" capability for faster and more complete searching
Improvements to RTL/Technology schematic viewers to speed viewing of top-level design
Improvements to Constraints Editor to support direct "spreadsheet-style" constraint entry
ISim GUI improvements
History of previous searches saved
–sourcelibdir switch added to ISim compiler (fuse) to emulate Cadence Verilog-XL “-y” behavior
What's New in Embedded Tools and IP
XPS Enhancements
Base System Builder support for dual-PIM in MPMC creates smaller designs when targeting Spartan devices
Embedded IP
MicroBlaze v7.20.b support
Documentation
Updated EDK Concepts, Tools, and Techniques Guide. With this updated guide, you can now create a design using the 11 versions of ISE and EDK.
What's New in DSP Tools and IP
System Generator
System Generator Enhancements
Support for Linux point-to-point Ethernet Hardware co-simulation
Support for QPro Virtex-4 Hi-Rel and QPro Virtex-4 radiation tolerant devices
Support for MATLAB 2009a
Xpower integration with System Generator
AccelDSP Synthesis Tool
Starting with this release, further development of the AccelDSP synthesis tool has been
discontinued. You can continue to use this version of the tool with ISE Design Suite 11.
The tool will not be included in ISE Design Suite 12.
What's New in CORE Generator and IP
New IP Cores
FPGA features and design
Clocking Wizard v1.2 - generates an HDL file with the clocking circuit customized based on user specification. The wizard automatically selects an appropriate clocking primitive and allows for the configuration of buffering, feedback, and timing parameters for the clocking network. In addition, it interactively aids the selection of correct attributes for the selected primitive and allows overriding of any wizard-calculated parameter.
Video and image processing
Video Timing Controller v1.0 - a general purpose video timing generator and detector. Automatic detection of horizontal and vertical front and back porches, sync pulses and active video pixels is provided along with sync and blank pulse polarity detection. Horizontal and vertical blanking and sync pulses are generated including support for programmable pulse polarity.
IP Core Updates
Support for Virtex-6 HXT, Virtex-6 Lower Power, and Virtex-5Q have been added to selected cores in this release.
A comprehensive listing of cores that have been updated in the 11.2 release can be viewed at www.xilinx.com/ipcenter/coregen/11_2_datasheets.htm.
For more information, refer to www.xilinx.com/ipcenter/coregen/updates_11_2.htm.
New CORE Generator Features
Automated core upgrade to latest version capability has been added for the following IP cores
FIFO Generator v5.2
Divider Generator v3.0
Floating Point Operator v5.0
FIR Compiler v5.0
- Fast Fourier Transform v7.0
What's New in ISE Design Suite 11.1
New ISE Design Suite Licensing and Product Configurations
The following describes changes in the ISE Design Suite 11:
Licensing for the ISE Design Suite is Now Managed by FLEXnet Publisher
Xilinx software products join select Xilinx IP cores in using FLEXnet licensing
Allows customers to track their design tool and IP usage with an industry standard licensing scheme
Software and almost all FLEXnet licensed IP products can now be downloaded and licensed from a single website
Licensing through IP Product Lounges is no longer necessary
CAD-tool or customer license administrators now have improved ability to manage Xilinx software and IP licenses from a single web-location
IP licensing procedures now merged with software licensing flow, which reduces the time it takes to obtain an IP license from several days to just a few hours, or even minutes, in some cases
Floating and triple-redundant license servers now supported
One license shared by multiple users provides a cost-effective solution where multiple users can leverage a single seat
Node-lock licenses may use Host IDs from an Ethernet MAC address, hard-drive serial number, or dongle-based FLEXids
IP node-lock licenses formerly supported only Ethernet MAC addresses
ISE Design Suite 11 Offers Configurations to Match your Design Methodology
ISE Design Suite: Logic Edition - complete toolset for your design and debug needs
Includes ISE Foundation™ design tool, ISE Simulator (ISim), PlanAhead™ design analysis tool, ChipScope™ Pro tool, ChipScope Pro Serial I/O Toolkit, and CORE Generator™ system
ISE Design Suite: Embedded Edition - complete flow featuring logic and embedded capabilities
Includes ISE Design Suite: Logic Edition plus Embedded Development Kit (EDK) comprised of Xilinx Platform Studio (XPS) and Software Development Kit (SDK)
ISE Design Suite: DSP Edition- complete flow featuring logic and digital signal processing (DSP) tools
Includes ISE Design Suite: Logic Edition plus System Generator for DSP and AccelDSP™ synthesis tool
ISE Design Suite: System Edition -includes all software products in the ISE Design Suite for a complete system-level design solution
All tools in ISE Design Suite: Logic Edition plus EDK, System Generator for DSP, and AccelDSP synthesis tool
What’s New in Logic Design Tools
The following describes what’s new in ISE Foundation, ISE WebPACK™ software, ISim, PlanAhead, ChipScope Pro, and ChipScope Pro Serial I/O Toolkit:
Reduced Runtime
Synthesis runtime improvements
XST runs 1.6x to 2x faster, depending on design size and complexity
Improvements made to the low-level optimization phase
Place and route runtime reduced by 46% across customer design suite
Multi-threading support added for place and route on Linux
Leverage multiple processors or cores on a single machine
SmartXplorer supports Load Sharing Facility (LSF) and Sun Grid Engine (SGE) compute farms on Linux
Spawns flow compiles on multiple hosts for timing closure
Compatible with existing compute farms (LSF and SGE)
Provides an easy to use timing closure tool by experimenting advanced options and collating results
Leverages new netlist optimizations options
Available at the command line or via Project Navigator
SmartXplorer also supports multiple processors and cores in a single machine on Windows
SmartGuide™ technology tuning for faster runtimes
Focus placed on design preservation rather than timing improvement
Completely redesigned ISim interface results in faster RTL simulation
Multi-processing is turned on by default in HDL compiler (fuse), which reduces compile time up to 2x
SecureIP for Synopsys VCS-MX , Cadence NC-Sim and Mentor Graphics ModelSim/QuestaSim
Faster simulation runtimes by leveraging the latest encryption methodology
Simulation models for Hard-IP such as PowerPC® processor, MGT, and PCIe® standard leverage this technology
Seamless to setup and use as compared to SmartModels
Usability Improvements
Project Navigator – improved look and feel, usability, and responsiveness
Improved direct access to ISE applications
Improved tool integration with automatic handling of source and constraint files from System Generator for DSP, XPS, and CORE Generator system
Support for ASCII project files for easier source control and direct user editing
Streamlined process tree and Design Summary make it easy to find tools and reports
Flexible window layouts allow you to customize Project Navigator to meet your needs
PlanAhead integration with Project Navigator
PlanAhead is now the single tool for floor planning and pin planning, replacing Floorplanner and PACE
PlanAhead is launched directly from within Project Navigator
PlanAhead constraints are automatically saved back to ISE project User Constraint File (UCF)
Full PlanAhead features and functionality available to all ISE users
ChipScope Pro integration within PlanAhead
Tighter integration allows users to insert ChipScope debug cores from within PlanAhead
ChipScope cores can be floorplanned with the rest of the design
Existing ChipScope core instances are automatically recognized
Tcl scripting supported for ChipScope VIO core
ChipScope Analyzer improvements
Bus creation and modification has been improved
Inserter project files (CDC) can be linked to bit files for automated signal annotation
Easier pin planning in ISE with integrated PinAhead technology
Supports both pre- and post synthesis phases
Allows part/package migration
Improved design rule checks (DRC) and simultaneous switching noise (SSN) checks
Enhanced design-oriented IBIS files
IBISWriter now supports DCI and differential I/O standards
New RTL / Technology Viewer with debug features
Faster schematic rendering
New features allow for extraction of logic cones and hiding contents
Timing Analyzer usability improvements
Component switching limits are now checked during place and route as well as timing analysis
Ability to specify multiple parameters for clock and I/O analysis: duty cycle, input jitter, valid duration, data arrival, clock edge/phase, etc
Link to DataSheet Delay names directly from timing reports for all architectures
Cross probing to FPGA Editor, including the complete clock path for offset constraints
Ability to print only selected section of timing reports
ISim GUI improvements
A new static waveform viewer is available to open static simulation
Crisp, new look and feel
Improved scrolling and zoom features
New ruler tool to ease measuring capabilities
Support for virtual buses
Ability to add copies of signals into the same waveform
PROM File Formatter redesigned
Single-pane interface shows all configuration data in one view
Built-in help explains each option and setting
Power Optimization
Dynamic power reduction
10% dynamic power reduction from place and route
Re-synthesis to minimize element switching on critical cones of logic (based on VCD or SAIF activity file)
Placement to minimize use of vertical clock spines
Clustering of high activity elements
Clock gating in MAP
Improved power estimation and analysis
Vectorless power estimation
Improved power analysis
Tune worst-case power estimation such that worst case will not under-estimate
Xilinx Power Estimator (XPE) provides an estimate of dynamic power reduction when using low power switches
Switching Activity Interface Format (SAIF) files can be generated by ISim
Reduced Memory Usage
30% reduction in memory for synthesis and place and route
Improved Project Navigator responsiveness and memory efficiency
Redesigned ISim interface reduces memory usage
Design Optimization Improvements
New goal-based optimization
Global optimization during place and route can be run in one of three modes: power, speed or area
XST gives improved area and performance
Better handling of BRAMs in byte-write enable mode
Improved processing of dual-port BROMs
Better register absorption for DSP blocks
Performance tuning has been improved for Virtex-5 devices
User Assistance Improvements
ISE Help
Easier to find information
Reorganized based on steps in the design flow
New sections added to assist with analyzing and optimizing design implementation results
ISim Help
Content rewritten to follow the software flow
ISim User Guide
The ISim User Guide is a new addition to the user assistance collection. It contains the same content as ISim Help and is available both in the software and on the Xilinx website.
Command Line Tools User Guide
Formerly known as the Development System Reference Guide, the document had a name refresh and is now the Command Line Tools User Guide. The document provides an overview of the Xilinx development system and information on command line implementation tools and options for both FPGA and CPLD devices.
Documentation Updates
Updates to the ISE books and online help are now delivered via the XilinxUpdate utility in the ISE software. To ensure you have the most recent copy of the ISE documentation installed on your system, run the XilinxUpdate utility using the Help > XilinxUpdate menu command. You can also get the latest documentation update in the Xilinx Download Center at www.xilinx.com/download.
What’s New in Embedded Tools and IP
The following describes what’s new in SDK, EDK, XPS, and embedded IP:
Software Development Kit (SDK)
SDK is now available as a standalone development tool
The larger ISE Design Suite installation is no longer required, significantly reducing required installation space
SDK now imports the hardware platform information from XPS
EDK contains one seat of SDK and one seat of XPS
SDK enhancements:
No requirements for location of SDK workspace
Automatically recognizes changes to hardware specification, and automatic resynch of software projects
Support for multiple software platforms and board support package (BSP) projects in a single workspace
Enhanced C/C++ Projects View
Simplified BSP configuration dialogs
Integrated creation of test programs
Enhanced list of test programs
Retargeting of software projects to different hardware systems
Support for software repositories
Integrated FPGA download capability
Safe mode debugging to trap unhandled exception conditions
Can now set breakpoints in program startup routines
Enhanced user documentation and built in cheat sheets (tutorials)
Datasheets for IP and drivers can be accessed via the design report included in the hardware handoff files
Ability to stop MicroBlaze™ processor v7.20.a when in a blocked state
Command line XMD now supports directory auto-completion and history
JRE version updated to 1.5
Enhanced import of software projects
System Generator integration support with SDK for software development
lwIP library updated
Xilinx Platform Studio (XPS)
XPS enhancements:
Base-system builder (BSB) creation of dual-PPC, dual-MicroBlaze, and mixed processor system
Automation of dual processor designs
Enables unique capabilities of using FPGAs with embedded processors
Exploits dual PPC Virtex devices
Enable higher system performance levels
New start up page for easier navigation of documentation and support pages
Ability to explicitly set simulator path to match ISE
New project archiver
Automation to create local copies of pcores
Integrated design summary page
New "Export Hardware Design to SDK" capability
Integration of MIG PHY generation for MPMC
Easy way to filter out bus interfaces and ports in System Assembly view to enable focus on specific portions of designs
Numbers associated with messages and ability to filter messages in Design Summary view
Address tab in System Assembly view shows processor instance specific address map
More instant feedback and DRCs within XPS during design modification
Comprehensive change log for embedded IPs spanning over multiple-versions of a given IP
Embedded software development features have been deprecated in XPS and will be removed in future release
Changes in the Clock Generator GUI will now automatically update resulting system changes
EDK/ISE Integration Improvements
Improved synchronization eliminates unnecessary recompilations of XPS projects
Embedded IP
MicroBlaze specific
Write-back caches
New atomic test and set instructions
Debug enhancements
MultiPort Memory Controller (MPMC)
Debug registers, provides software control over PHY
MIG 3.0 PHY support
MIG PHY generation now integrated in XPS
MicroBlaze and MPMC optimizations
Dual, smaller footprint Cache Link interface
Direct MicroBlaze access to MPMC control registers
OPB and PLBv34 cores are deprecated (except bridges and buses)
xps_ll_temac
Reduced resources - now uses fewer BUFGs and BRAMs
Improved RX performance through more efficient FIFO full management
plbv46_pcie
Split out block plus wrapper into encrypted helper core
Top level is now open source
usb2_device core
Faster performance
Built-in DMA
See individual core history files for more updates
What’s New in DSP Tools and IP
The following describes what’s new in System Generator, AccelDSP, and DSP IP:
Both System Generator for DSP and AccelDSP support MATLAB® R2008 software.
System Generator for DSP
Linux support
Red Hat Enterprise Linux 4 WS (32 and 64-bit)
Integration with SDK
System Generator can launch SDK to modify software running on an embedded processor
IP lifecycle
Old versions of versioned IP have been superseded
Warning message generated for any Xilinx IP core that is not the latest version
Summary report generated for designs that contain IP that is not the latest version
Updated design examples
New and updated examples using the latest IP and targeting the latest devices
Integration with XReport
XReport can be launched directly from System Generator
New/Updated IP
New blocks with support added for Virtex-5 and extended Spartan-3A devices - CORDIC 4.0, Complex Multiplier 3.0
Updated basic building blocks to version 11.0 - Adder Subtractor, Accumulator, Binary Counter, Multiplier, Addressable Shift Register
Updated memory blocks to use Block Memory Generator 3.1, Distributed Memory Generator 4.1 and FIFO Generator 5.1 –Single port RAM, Dual Port RAM, ROM, FIFO, Shared Memory, To FIFO and From FIFO
AccelDSP Synthesis Tool
Higher performance design examples
Updated to target latest silicon and implement at higher frequencies
Enhanced Fixed-Point Report to aid in achieving higher quality of results (QoR)
New tabs can be sorted to show details on largest operators, largest arrays, and architecture information
LogiCORE™ system performance enhancements
LogiCORE usage is now the default for the VHDL flow
New support for adder and subtractor
New GUI support for LogiCORE parameters
New support to add more than one register to all inputs and outputs for higher performance
Memory map enhancements
New option "ram_threshold" to automatically map arrays to RAM
"sp_sync_ram" and "sp_sync_rom" have been removed and replaced with "dp_sync_ram"
New option "array_access_guard" to control scheduling optimizations
Tab and references for AccelWare™ reference design have been removed
All MATLAB functions previously supported via AccelWare are still supported via AccelDSP
What's New in CORE Generator and IP
The following describes what’s new in CORE Generator and IP cores:
New IP Cores
Math functions
Multiply Adder v2.0 - performs multiplication of two operands and adds (or subtracts) the full-precision product to a third operand using Xtreme DSP™ solution slices
Multiply Accumulator v2.0 - accepts two operands, a multiplier and a multiplicand, and produces a product that is added (or subtracted) to the previous result using Xtreme DSP slices
Video and image processing
Color Correction Matrix v1.0 - a highly optimized constant coefficient matrix multiplier core using Xtreme DSP slices for correcting color in a video data stream
Color Filter Array Interpolation v1.0 - a high quality hardware block used for interpolating between RAW sensor data and the RGB color domain
Defective Pixel Correction v1.0 – IP optimized for "real-time" operation for automatic detection and correction of defective pixel with interpolated values based on neighboring pixels
Gamma Correction v1.0 - provides customers with a fully tested and optimized hardware block for manipulating the values on a per pixel basis for gamma adjustment
Image Processing Pipeline v1.0 - dedicated hardware core to automatically generate an image from a CMOS/CCD sensor from a given set of parameters which includes a wide range of features and optimizations
Video Scaler v1.0 - a high-quality scaling solution for customers implementing designs ranging from polyphase to linear interpolation for up and down scaling
IP Core Updates
A comprehensive listing of cores that have been updated in this release can be viewed at www.xilinx.com/ipcenter/coregen/11_1_datasheets.htm
For more information see www.xilinx.com/ipcenter/coregen/updates_11_1.htm
New CORE Generator Features
IP catalog enhancements
IP catalog visible within Core Generator before opening a project
Enhanced keyword search lists results both by functional category or by name
IP core scheduled to be “Superseded” by newer versions and cores scheduled to be “Discontinued” can be viewed by selecting “All IP Versions”
IP cores supported for selected device family can be viewed by selecting “Only IP Compatible with chosen part”
Enhanced IP output
Generation of ISE project files to facilitate integration and management of IP cores in Project Navigator
Selected video and image processing cores generate “EDK Pcore” to facilitate integration and management of IP cores within XPS projects
Automated core upgrade to latest version capability is available for the following IP cores: Adder Subtracter, Accumulator, Binary Counter, Block Memory Generator, Complex Multiplier, CORDIC, Multiplier and RAM-based Shift Register
Capability to allow regeneration of all project IP cores with different project settings than were originally used to generate the core
Technical Support
For Technical Support Issues, visit www.xilinx.com/support where features such as the Answers Database and User Forums may help to resolve your issue. If your issue can not be resolved on the support site, a WebCase can be created and a Technical Support engineer can further assist you.
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