Running the Generate Programming File Process for FPGAs
run the Generate Programming File process after your FPGA design is
completely placed and routed (PAR). The Generate Programming
File process runs BitGen, the Xilinx® bitstream generation program,
to produce a bitstream (BIT or ISC file) for Xilinx device configuration.
Note Bitstream generation automatically incorporates software
application data from the ELF files that are part of the project.
The programming file is saved in your project directory.
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