Running the Generate Programming File Process for FPGAs
You can run the Generate Programming File process after your FPGA design is completely placed and routed (PAR). The Generate Programming File process runs BitGen, the Xilinx® bitstream generation program, to produce a bitstream (BIT or ISC file) for Xilinx device configuration.
Note Bitstream generation automatically incorporates software application data from the ELF files that are part of the project.
To Run the Generate Programming File Process
  1. In the View pane of the Design panel, select Implementation.Image
  2. In the Hierarchy pane, select the top module Image.
  3. Optional. In the Processes pane, right-click the Generate Programming File process, and select Process Properties to set properties for the process in the following dialog boxes. Image
  4. In the Processes pane, double-click Generate Programming File.
The programming file is saved in your project directory.
After running this process, you can perform any of the following:
  • Check the report generated by the Generate Programming File process. Image
  • Generate a PROM or ACE file. Image
  • Generate a Boundary Scan (JTAG) file. Image
  • Configure or program a target device. Image
Note For information on Xilinx device configuration, see the Configuration and Programming Overview.

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