Constraints Editor
Constraints Editor Overview
Constraints are instructions placed on instances or nets in an FPGA or CPLD schematic or textual entry file such as VHDL or Verilog. Constraints specify placement, implementation, naming, signal direction, and timing considerations for timing analysis and for design implementation. In Xilinx® tools, logical constraints are placed in the User Constraints File (UCF).
The Constraints Editor lets you do the following:
  • Specify global timing constraints (PERIOD, OFFSET IN, OFFSET OUT, and operating conditions). Image
  • Specify Groups on which to apply constraints. Image
    Note You can also specify groups when you need them rather than trying to anticipate all groups that you might want to use.
  • Specify input timing constraints (OFFSET IN) on pad groups or pad nets.Image
  • Specify output timing constraints (OFFSET OUT) on pad groups or pad nets.Image
  • Specify timing exceptions for paths or nets. Image
  • Specify miscellaneous constraints. Image
  • Create a Constraint Audit File in Constraints Editor.Image
  • Create a Constraint Audit File from the command line.Image
Opening Constraints Editor will automatically open the existing User Constraints File (UCF) in the Workspace or create a new UCF if necessary.
Note For instructions on how to initialize memory and registers, see the Synthesis and Simulation Design Guide.
See Also

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