Constraints Editor Overview
Constraints are instructions placed on instances or nets in an
FPGA or CPLD schematic or textual entry file such as VHDL or Verilog.
Constraints specify placement, implementation, naming, signal direction,
and timing considerations for timing analysis and for design implementation.
In Xilinx® tools, logical constraints are placed in the User Constraints File (UCF).
The Constraints Editor lets you do the following:
Opening Constraints Editor will automatically open the existing User Constraints File (UCF) in
or create a new UCF if necessary.
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